PCIe (Peripheral Component Interconnect Express) equipment and detection method thereof

A technology of internal interconnection and equipment, applied in the field of mobile communication, can solve problems such as CPU hanging, achieve the effect of improving reliability, reducing the scope of isolation, and reducing impact

Inactive Publication Date: 2016-06-22
HUAWEI TECH CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] The invention provides a PCIe device and a detection method thereof, which ar

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  • PCIe (Peripheral Component Interconnect Express) equipment and detection method thereof
  • PCIe (Peripheral Component Interconnect Express) equipment and detection method thereof
  • PCIe (Peripheral Component Interconnect Express) equipment and detection method thereof

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Embodiment Construction

[0035] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

[0036] In order to facilitate the understanding of the embodiments of the present invention, further explanations will be given below with specific embodiments in conjunction with the accompanying drawings, which are not intended to limit the embodiments of the present invention.

[0037] The PCIe port in the PCIe device is connected to the EP device. Since both the root node RP in the CPU of the PCIe device and the downstream port DP in the PCIeSwitch can be connec...

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Abstract

The invention relates to PCIe (Peripheral Component Interconnect Express) equipment and a detection method thereof. The PCIe equipment comprises a PCIe port, wherein the PCIe port can be in a DP (Downstream Port) of a PICe bridge and also can be in a RP (Root Point) of a CPU (Central Processing Unit). One example comprises the following steps: a PCIe kernel unit receives a transmission layer message issued from the CPU or an UP (Upstream Port) and issues the message to an EP (End Point); an exception detection unit detects a process that the port issues the message to the EP, identifies whether the process has message retransmission exception, such as ACK/NAK (Acknowledge/Negative Acknowledge) message exception or fluid control credit value update exception or not, and the exception detection unit outputs a hardware chain scission enable signal when no credit value exception is in the presence; and a hardware chain scission unit disconnects the link of the PCIe port and the EP according to the signal. The embodiment of the invention detects and processes ACK/NAK message or fluid control credit value update which can not be perceived but can cause the exception including CPU crash so as to guarantee that the CPU can normally work, and the reliability of the PCIe system and the compatibility of the system on a drive program can be improved.

Description

technical field [0001] The invention relates to the field of mobile communication, in particular to a PCIe device internally interconnected with peripheral components and a detection method thereof. Background technique [0002] With the widespread use of the Peripheral Component Interconnect Express (PCIe) protocol in storage, computing and other fields, its requirements for system reliability are getting higher and higher; in order to improve system reliability, the PCIe protocol defines a series of errors The detection and processing mechanism is used to improve the impact of IO device exceptions on the host, but the PCIe protocol still has insufficient understanding of the severity of some errors, and the CPU is also imperfect in handling some errors. [0003] Currently, when an IO device is abnormal, it may cause a root node (RootPoint, RP) of the PCIe device or a downstream port (DownstreamPort, DP) of the PCIe bridge PCIeSwitch to be abnormal, wherein the PCIeSwitch c...

Claims

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Application Information

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IPC IPC(8): G06F11/07
CPCG06F11/0793G06F11/0721G06F11/0757
Inventor 张浩鹏吴沛
Owner HUAWEI TECH CO LTD
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