A half-selective interference cancellation structure for sram based on hierarchical bit line structure

Abstract

The invention discloses a static random access memory (SRAM) half-select disturb elimination structure based on a hierarchical bit line structure. The SRAM half-select disturb elimination structure based on the hierarchical bit line structure comprises a storage array which has the hierarchical bit line structure; each storage unit of the storage array has a single reading operation branch; each column of the storage array is divided into a plurality of sub-modules. According to the SRAM half-select disturb elimination structure based on the hierarchical bit line structure, by utilizing virtual ground wire control, a ground wire of the reading operation branch of each storage unit in each sub-module is singly guided out, and is uniformly connected with an actual ground wire through a ground wire control switch; additionally, column selection signals Col of a corresponding column of each sub-module control a conduction state of each ground wire control switch, and a bit line discharge path of an unselected column unit during a reading operation is switched off, so that static power consumption caused by half select disturb is completely eliminated; however, due to utilization of a local bit line suspension technology, unselected column is forced to locally suspend in a writing operation, so that a short circuit discharge path is eliminated; meanwhile, the disturbance of local bit lines to a half-select unit is effectively reduced, so that unit robustness is improved, and noise margin is increased.

Description

technical field [0001] The invention relates to the technical field of semiconductor integrated circuits, in particular to an SRAM (Static Random Access Memory, static random access memory) semi-selective interference elimination structure. Background technique [0002] With the development of technology and the change of lifestyle, people's demand for health aids such as implanted biochips and wearable devices is increasing. Most of these devices are powered by batteries, and in order to prolong their service life, the internal memory SRAM is required to be able to operate with lower power consumption. However, since the storage arrays are mostly arranged using the interleaving rule, serious half-selection interference problems will occur when the SRAM is working. Such as figure 1 As shown, during the read and write operations, the unselected cells are disturbed by the precharge level of the bit line, and the voltage of the storage node Q rises, which not only leads to se...

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Problems solved by technology

[0005] As mentioned above, although researchers have proposed a variety of novel solutions from different perspectives, most of them are not ideal, and the semi-selection problem is still unresolved, which still seriously affects the power consumption and robustness of SRAM circuits.

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