32results about How to "Eliminate Static Power Consumption" patented technology

The invention discloses a low-dynamic maladjusted high-speed low-power consumption comparator circuit. The circuit comprises a first-stage pre-amplifying circuit and a second-stage positive-feedback latch circuit; the comparator circuit controls a comparison stage and a reset stage of the comparator circuit by adopting a clock signal; the comparator circuit is located at the comparison stage whenthe clock signal is located at high level, a pair of differential input signals are respectively amplified through the first-stage pre-amplifying circuit so as to form a pair of primary differential signals; the second-stage feedback latch circuit inversely amplifies a pair of primary differential signals and forms a pair of secondary differential signals, and performs the positive feedback latching on the secondary differential signals so as to obtain a pair of differential output signals. By adopting a tail current source biased by a bias voltage and a cascade switch tube controlled by the clock signal, the static power consumption is eliminated, the stability on the tube over-driving voltage by the differential input is guaranteed, and the dynamic maladjustment is effectively reduced.

The invention discloses an XOR/XNOR gate circuit based on FinFET devices. The circuit comprises a first FinFET transistor, a second FinFET transistor, a third FinFET transistor, a fourth FinFET transistor, a fifth FinFET transistor, and a sixth FinFET transistor, the first FinFET transistor and the fourth FinFET transistor are both P-type FinFET transistors, the second FinFET transistor, the third FinFET transistor, the fifth FinFET transistor, and the sixth FinFET transistor are all N-type FinFET transistors, the first FinFET transistor and the fourth FinFET transistor are both low-threshold FinFET transistors, the second FinFET transistor, the third FinFET transistor, the fifth FinFET transistor, and the sixth FinFET transistor are all high-threshold FinFET transistors, the numbers of the fins of the first FinFET transistor and the fourth FinFET transistor are both 1, and the numbers of the fins of the second FinFET transistor, the third FinFET transistor, the fifth FinFET transistor, and the sixth FinFET transistor are all 2. The circuit is advantageous in that the logic function is correct, the circuit area is small, the time delay is short, the power consumption is low, and the consumption-delay product is small.

The invention discloses a voltage detection circuit which comprises a voltage divider circuit and a comparator. The voltage divider circuit includes a first capacitor and a second capacitor. A first end of the first capacitor is connected with a reference voltage, and a second end of the first capacitor is connected with a supply voltage through a first switch. A first end of the second capacitor is connected with the reference voltage through a second switch and connected with a ground potential through a third switch, and a second end of the second capacitor is the output end of the voltage divider circuit, connected with a first end of the comparator, and connected with the reference voltage through a forth switch. The second end of the first capacitor is connected with the second end of the second capacitor through a fifth switch. The voltage detection circuit can reduce the occupation space of the circuit on a chip, completely cancel the static power consumption of the circuit, thereby reducing the power consumption of the circuit, and guarantee that the high voltage dividing precision of the circuit.

The invention discloses a single track current mode one bit full adder based on a FinFET device. The single track current mode one bit full adder comprises a bias circuit, a summation output circuit, and a carry output circuit. The summation output circuit comprises a third P-type FinFET pipe; a fourth P-type FinFET pipe and a fourth N-type FinFET pipe, which are respectively connected with the third P-type FinFET pipe; a fifth N-type FinFET pipe and a sixth N-type FinFET pipe, which are parallely connected together; a seventh N-type FinFET pipe; a ninth N-type FinFET pipe and a tenth N-type FinFET pipe, which are parallely connected together. The fourth N-type FinFET pipe is connected with the fifth N-type FinFET pipe and the sixth N-type FinFET pipe, which are parallely connected together. The seventh N-type FinFET pipe is connected with the fifth N-type FinFET pipe and the sixth N-type FinFET pipe, which are parallely connected together, and is connected with the ninth N-type FinFET pipe and the tenth N-type FinFET pipe, which are parallely connected together. By adopting a differential single track current mode structure, the N-type FinFET pipes in the pull-down network of the single track current mode adopt the parallel connection structures to realize a multi-input NOR function, and the serial connection configuration of the N-type FinFET pipes is prevented, and therefore circuit performance is optimized, and the circuit can still work normally under conditions of standard voltage and superthreshold.

The invention relates to a continuous 3-order sigma-delta modulator circuit (11) based on an active resistance-capacitance integrator. The circuit comprises a first integrator (111), a second integrator (112), a comparator (113), a first trigger (114), a second trigger (115), a first digital to analog converter (116), a second digital to analog converter (117), a third digital to analog converter (118), a fourth digital to analog converter (119), a logical OR circuit (120), a first inverter (121) and a second inverter (122). By adopting the circuit disclosed by the invention, the power consumption of the circuit can be significantly reduced.

The invention provides a low-power-consumption constant conduction time timing circuit design method and timing circuit. An RC circuit is adopted for timing and the static power consumption of the timer is eliminated. The concrete structure is that the timing circuit comprises a fourth PMOS transistor M4 of which the source electrode is connected with input voltage VIN, the gate electrode is connected with the conduction time control end TON_CONTROL and the drain electrode is connected with one end of a fourth resistor R4. The other end of the fourth resistor R4 is connected with one end of afourth capacitor C4. The other end of the fourth capacitor C4 is grounded. The input negative electrode of a comparator VCMP is connected with reference voltage, and the input positive electrode is connected between the fourth capacitor C4 and the fourth resistor R4. According to the circuit under the design method, the static power consumption of the constant conduction time timing circuit can beeliminated so that the power consumption of the whole circuit can be reduced, and the circuit structure is simple and the cost is low.

The invention discloses a discrete threshold voltage comparator with zero static power consumption. The discrete threshold voltage comparator comprises a first transistor and a plurality of parallel threshold value adjustment branches, wherein each threshold value adjustment branch is connected with the first transistor and a digital enable bit of the voltage comparator, and each threshold value adjustment branch adjusts a threshold voltage of the voltage comparator according to a digital control signal received by the digital enable bit. According to the discrete threshold voltage comparator , the plurality of parallel threshold value adjustment branches are arranged in the voltage comparator, and the threshold voltage of the voltage comparator is adjusted based on the digital control signal received by the digital enable bit, thus the digital control of the threshold voltage of the voltage comparator is realized; and since the voltage comparator utilizes digital control for adjusting the threshold voltage, the threshold voltage is eliminated, the discrete threshold voltage comparator with zero static power consumption and adjustable threshold voltage values is implemented, reset operation is avoided and the system dead time is eliminated.

The invention requests to protect a low-power-consumption Binary-Search ADC system based on a full-dynamic structure. The low-power-consumption Binary-Search ADC system comprises a bootstrap samplingcircuit, a full-dynamic comparator array with a pre-amplifier and a decoder array, and the bootstrap sampling circuit comprises a charge pump circuit, a bootstrap sampling switch and a sampling capacitor; a decision array comprises a dynamic preamplifier, a dynamic comparator and a rear-end decoder array of each stage. The invention aims to enable all main modules in the circuit to be improved into a dynamic structure, the circuit does not work when no control time sequence is input, and most of time sequence signals for controlling the circuit to work are generated by the circuit structure, so that the power consumption is further reduced. The innovation point is that compared with a traditional architecture, the system has a remarkable effect of reducing the circuit power consumption based on a full-dynamic structure. According to the full-dynamic structure, the power consumption of the circuit can be reduced, the offset voltage influence of the circuit is reduced by the dynamic amplifier, and the precision is ensured.