A cmos addition unit

An addition unit, the eleventh technology, applied in the field of CMOS addition units, can solve problems such as circuit performance deterioration, circuit consumption, and multi-energy consumption, and achieve the effects of eliminating leakage, speeding up operation, and improving circuit speed

Active Publication Date: 2017-04-26
无锡三聚阳光知识产权服务有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the dynamic logic circuit itself also has some factors that lead to poor circuit performance: such as charge leakage effects, charge sharing problems, etc. These effects often cause the circuit (especially at high frequencies) to consume more energy. In the environment of large-scale integrated circuit design, there will be huge losses

Method used

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Examples

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Embodiment

[0017] Example: such as figure 1 As shown, a CMOS addition unit includes a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth PMOS transistor P5, a sixth PMOS transistor P6, a first NMOS transistor N1, the second NMOS transistor N2, the third NMOS transistor N3, the fourth NMOS transistor N4, the fifth NMOS transistor N5, the sixth NMOS transistor N6, the seventh NMOS transistor N7, the eighth NMOS transistor N8, the ninth NMOS transistor N9, The tenth NMOS tube N10, the eleventh NMOS tube N11, the twelfth NMOS tube N12, the thirteenth NMOS tube N13, the fourteenth NMOS tube N14, the fifteenth NMOS tube N15, the sixteenth NMOS tube N16, the tenth The seventh NMOS transistor N17, the eighteenth NMOS transistor N18, the nineteenth NMOS transistor N19, and the twentieth NMOS transistor N20, the source of the first PMOS transistor P1, the source of the second PMOS transistor P2, and the third PMOS transistor P3 ...

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PUM

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Abstract

The invention discloses a CMOS addition unit, which uses the first PMOS transistor and the fourth PMOS transistor as pre-charging transistors, uses the second PMOS transistor and the fifth PMOS transistor as anti-charge leakage transistors, and consists of the third NMOS transistor and the fourth NMOS transistor. tube, the fifth NMOS tube, the seventh NMOS tube and the eighth NMOS tube form the PDN Carry evaluation network, which consists of the twelfth NMOS tube, the thirteenth NMOS tube, the fourteenth NMOS tube, the fifteenth NMOS tube, the tenth NMOS tube Six NMOS tubes, the seventeenth NMOS tube and the eighteenth NMOS tube form the PDN Sum, the first NMOS tube, the second NMOS tube, the sixth NMOS tube, the tenth NMOS tube, the eleventh NMOS tube and the nineteenth NMOS tube As evaluation transistors respectively, the third PMOS transistor and the sixth PMOS transistor, the ninth NMOS transistor and the twentieth NMOS transistor constitute an inverter respectively; the advantage is that the delay and power consumption-delay product of the overall circuit are improved, It has small circuit delay and power-delay product at both low frequency and high frequency operation.

Description

technical field [0001] The invention relates to an adding unit, in particular to a CMOS adding unit. Background technique [0002] As the basic computing unit of electronic systems, the full adder is widely used in many VLSI systems. For example, in high-performance microprocessors and DSP processors, the computing power of a full adder is very important. The operation of a full adder is often in the critical path of high-performance processor system components, especially in the arithmetic logic unit, the operation performance of a full adder plays a very critical role in the performance of the processor. As the computing speed of the microprocessor becomes faster and faster, the demand for a fast one-bit full adder is also higher and higher, and its speed, power consumption, and area performance will directly affect the overall performance of the entire integrated circuit. [0003] The circuit types of the existing adding unit mainly include static logic and dynamic logic...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03K19/20
Inventor 胡建平程伟
Owner 无锡三聚阳光知识产权服务有限公司
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