CMOS low-power consumption, low offset voltage, low return-stroke noise comparator

Abstract

The invention discloses a CMOS comparator with low power consumption, low offset voltage and low return noise, belonging to the technical field of the radio communication system. The CMOS comparator comprises a preposing amplifier, a pair of switch tubes, a positive feedback latch unit, a CMOS phase inverter and an SR latch unit, wherein the preposing amplifier adopts a PMOS tube to serve as the input differential pairs, a diode is connected with an NMOS tube and is connected with a circuit structure which is in positive feedback connection with the NMOS tube in parallel to serve as the load so as to reduce the offset voltage of the comparator; the pair of the switch tubes is inserted between the preposing amplifier and the positive feedback latch unit so as to reduce the return noise of the comparator; and the positive feedback latch unit adopts a cross-coupling CMOS inverter circuit structure, a reset pipe is connected between regenerating nodes, thereby not only reducing the power consumption but also increasing the regenerating speed. The comparator has good properties of low power consumption, low offset voltage and low return noise, does not need to adopt the offset cancelingtechnique, and can be widely applied to a low power consumption high-speed AD converter with 6 to 8 medium and high accuracy of a radio communication system.

Description

technical field [0001] The invention belongs to the technical field of wireless communication systems, and in particular relates to a CMOS voltage comparator, which is applied to a comparator with low power consumption, low offset voltage and low backhaul noise for analog-to-digital converters of portable equipment. Background technique [0002] In the front-end receivers of many contemporary wireless communication systems, high-speed, high-resolution analog-to-digital converters are required. For battery-powered portable device applications, the analog-to-digital converters are very demanding on power consumption. The wireless communication industries of various countries are committed to Research and design of high-speed, high-resolution, low-power analog-to-digital converters. As we all know, the comparator is the core circuit module of all analog-to-digital converters, and its characteristics such as offset voltage, power consumption, return noise, and comparison speed w...

AI Technical Summary

Problems solved by technology

H.Fiedler, et al., "A 5-bitbuilding block for 20MHz A / D converters," IEEE J.of Solid-State Circuits, vol.16, proposed a typical static latch comparator as figure 1 As shown, although the backhaul noise is low, there are obvious disadvantages: ① There are two DC paths from the power supply to the ground, and the power consumption is relatively large; rate limitation and low working speed; ③Using NMOS transistors as input differential pairs and diode-connected PMOS transistors as load circuit structure, not only the gain is low, but the contribution of positive feedback latch offset voltage is large, so its accuracy is limited to 6Bit

However, due to the leakage current of the switch made by the integrated process, it is easy to cause capacitor leakage, and the offset cancellation must be refreshed on time. The refresh process either increases the cost of the clock, or the control of the clock phase is complicated, and it is difficult to obtain a high conversion speed.

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