The application provides a computing device, a
chip and a method. The computing device comprises at least one compression unit, which is used for summing four-way input signals to obtain a first carry
signal and a first sum
signal; the compression unit comprises a carry
logic gate and a sum
logic gate; wherein the carry
logic gate is used for summing two-way carry input signals to obtain a carry value, and inverting the carry value to obtain one-way carry output
signal; the sum logic gate is used for summing two-way sum input signals to obtain a first sum value, and obtaining one-way sum output signal according to the size of the first sum value. By introducing the carry logic gate and the sum logic gate required for carry calculation, the maximum
delay path length of the circuit is reduced, the
power delay product of the compression unit is reduced, and the
circuit performance is improved.