34 results about "Power–delay product" patented technology

An electronic load device provided for testing an OT (power supply to be tested) and the working bandwidth is regulated and set according to the output impedance of the OT. The electronic load device comprises a CPU, an impedance-bandwidth table, a voltage-current measurement unit, a power stage and a control module. Firstly, a current pulled out from the OT to the power stage is called by the CPU. Thereafter, an output impedance of the OT is measured by the voltage-current measurement unit and analysis by the CPU. Next, a working bandwidth of the electronic load device is regulated and set by the control module according to the output impedance and the impedance-bandwidth table.

The invention discloses a ternary carbon nanotube successive approximation analog-to-digital converter, which comprises a latch comparator, a successive comparison logic circuit, a control circuit, a first capacitor array and a second capacitor array, and the output of the lock comparator terminal is connected with the input end of the successive comparison logic circuit, and the output end of the successive comparison logic circuit is connected with the control circuit, the first capacitor array and the second capacitor array are three-valued capacitor arrays, and the first capacitor array and the second capacitor array are controlled by the control circuit The capacitor array is connected to three different voltages, which realizes the charging and discharging operation of different capacitor arrays, effectively avoids the invalid operation of the switch, and greatly reduces the power consumption of the circuit. The latch comparator utilizes the high-speed and low-power consumption characteristics of CNFET , use CNFET to design, further reduce energy consumption and power delay product; the advantages of energy consumption and power delay product are small, which is of positive significance for further research on larger-scale low-power three-valued successive approximation analog-to-digital converters.

The invention discloses a FinFET device-based full-swing single-end read storage unit. The unit comprises a write word line, a writ bit line, an inverted write bit line, a read word line, a read bit line, a first FinFET, a second FinFET, a third FinFET, a fourth FinFET, a fifth FinFET, a sixth FinFET, a seventh FinFET, an eighth FinFET and a ninth FinFET, wherein the first FinFET, the second FinFET and the seventh FinFET are low-threshold P-type FinFETs; the third FinFET, the fourth FinFET, the fifth FinFET, the sixth FinFET and the ninth FinFET are low-threshold N-type FinFETs; and the eighth FinFET is a high-threshold N-type FinFET. The unit has the advantages that under the condition of not influencing a circuit function, the delay, the power consumption and a power-delay product are all relatively small, a data error does not occur during read operation, and the circuit stability is relatively high.

The invention discloses a controllable diode bootstrap adiabatic circuit and a four-level inverter / buffer. The controllable diode bootstrap adiabatic circuit comprises a first PMOS tube, a second PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, and a sixth NMOS tube. The four-level inverter / buffer comprises four controllable diode bootstrap adiabatic circuits. The advantages are as follows: a smaller number of MOS tubes are used, the circuit structure is simple, and the time delay and power consumption are reduced; and the fifth NMOS tube and the sixth NMOS tube constitute a controllable diode feedback path between the output end and the clock end of the controllable diode bootstrap adiabatic circuit, so that energy can be fully recycled, and the time delay, power consumption and power-delay product are smaller on the basis that the circuit performance is not affected.

The invention discloses a short-pulse type D trigger based on FinFET device. The short-pulse type D trigger comprises a first FinFET tube, a second FinFET tube, a third FinFET tube, a fourth FinFET tube, a fifth FinFET tube, a sixth FinFET tube, a first phase inverter, a second phase inverter, a third phase inverter, a fourth phase inverter, a fifth phase inverter, a sixth phase inverter, a seventh phase inverter, a seventh phase inverter, an eighth phase inverter, a ninth phase inverter, a tenth phase inverter, a first two-input NOR gate, a first two-input XOR gate and a second two-input XOR gate, wherein each of the first two-input NOR gate, the first two-input XOR gate and the second two-input XOR gate is provided with a first input, a second input and an output end; the short-pulse type D trigger has the advantages that the number of the FinFET tube is reduced, the circuit delay and the circuit area are further optimized since the series connection of the transistor is reduced; therefore, the circuit area, the time delay, the power consumption and the power delay product are small under the condition of not influencing the circuit performance.

The invention relates to a power-aware dynamic adaptive on-chip network threshold routing method, which predicts the load status of the on-chip network by using the adaptive threshold and the corresponding dynamic threshold step size. By adopting the adaptive threshold variable, the non-minimum route is selected only when needed, and the over-selection of non-minimum routes by the algorithm will cause a large amount of additional energy consumption; the application threshold step size variable will be adjusted according to the global network situation Change in order to control the magnitude and speed of threshold change; provide a reasonable routing algorithm for the development and application of dragonfly topology. Experimental results confirm that compared with the UGAL‑LVC‑H routing algorithm, the method of the present invention can save an average of 6.53% (n=4) and 5.93% (n=8) respectively on the power delay product, indicating that the dynamic self-adaptation of the power perception The network-on-chip threshold routing algorithm is a potential alternative to the dragonfly topology routing algorithm.

The invention discloses an adiabatic PAL-2N structure type JK flip-flop based on Fin-FET devices, comprising a first P-type Fin-FET, a second P-type Fin-FET, a third P-type Fin-FET, a fourth P-type Fin-FET, a first N-type Fin-FET, a second N-type Fin-FET, a third N-type Fin-FET, a fourth N-type Fin-FET, a fifth N-type Fin-FET, a sixth N-type Fin-FET, a seventh N-type Fin-FET, an eighth N-type Fin-FET, a ninth N-type Fin-FET, a tenth N-type Fin-FET and an eleventh N-type Fin-FET. The advantage is that under the condition that the circuit performance of the adiabatic PAL-2N structure type JK flip-flop is not affected, the number of Fin-FETs is reduced, the circuit area is reduced significantly, and the time delay, power consumption and power-delay product are reduced significantly.

The invention discloses a FinFET device-based unit line non-symmetric storage unit. The unit comprises a bit line, a write word line, a read word line, a first FinFET, a second FinFET, a third FinFET, a fourth FinFET, a fifth FinFET, a sixth FinFET, a seventh FinFET, an eighth FinFET and a ninth FinFET, wherein the first FinFET and the seventh FinFET are low-threshold P-type FinFETs; the second FinFET, the fourth FinFET, the fifth FinFET, the sixth FinFET, the eighth FinFET and the ninth FinFET are all low-threshold N-type FinFETs; and the third FinFET is a high-threshold P-type FinFET. The unit has the advantages that under the condition of not influencing circuit performance, the delay, the power consumption and a power-delay product are all relatively small, the noise margin during write operation is relatively large, and the circuit function stability is relatively high.

The invention discloses a current-mode RM NOR-XOR unit based on a FinFET device. The current-mode RM NOR-XOR unit comprises the first P-type FinFET tube, the second P-type FinFET tube, the first N-type FinFET tube, the second N-type FinFET tube, the third N-type FinFET tube, the fourth N-type FinFET tube, the fifth N-type FinFET tube and the sixth N-type FinFET tube, wherein the first P-type FinFET tube and the second P-type FinFET tube are respectively the low-threshold P-type FinFET tube; the first N-type FinFET tube, the third N-type FinFET tube and the fourth N-type FinFET tube are respectively the high-threshold N-type FinFET tube; the second N-type FinFET tube, the fifth N-type FinFET tube and the sixth N-type FinFET tube are respectively the low-threshold N-type FinFET tube. The current-mode RM NOR-XOR unit disclosed by the invention has the advantage that the circuit area, the time delay, the power consumption and the power delay product are small on the basis of the correct logic function.