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2 results about "Power–delay product" patented technology
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In digital electronics, the power–delay product (PDP) is a figure of merit correlated with the energy efficiency of a logic gate or logic family. Also known as switching energy, it is the product of power consumption P (averaged over a switching event) times the input–output delay or duration of the switching event D. It has the dimension of energy and measures the energy consumed per switching event.
Sigma-delta adc down-sampling digital filter floating point coefficient quantization unit design method
The application discloses a kind of Σ-ΔADC downsampling digital filter floating point coefficient fixed-point unit design method, with all-digital implementation, fusion is based on the optimal coding of graph theory, hybrid coding combination and multiplication-addition operation optimization technique.By the hybrid coding method based on graph theory, multiplication-addition law operation hardware resource is reduced, operation speed is improved, and while guaranteeing the slight drop of delay, the area and power consumption are significantly optimized.In addition, the optimization carry chain rearrangement algorithm is used to maximize the fanout number of adder and the efficiency of connection.Compared with the traditional floating point coefficient fixed-point encoding and adder method, the present application can effectively realize the multiplication-addition operation optimization of downsampling filter in Σ-ΔADC digital module, significantly reduce the power delay product on the basis of keeping similar area, significantly enhance the comprehensive performance of downsampling digital filter floating point coefficient fixed-point unit, and be suitable for multiplication-addition operation optimization of downsampling filter in Σ-ΔADC digital module.
Owner:XI AN JIAOTONG UNIV
A computing device, chip, and method
The application provides a computing device, a chip and a method. The computing device comprises at least one compression unit, which is used for summing four-way input signals to obtain a first carry signal and a first sum signal; the compression unit comprises a carry logic gate and a sum logic gate; wherein the carry logic gate is used for summing two-way carry input signals to obtain a carry value, and inverting the carry value to obtain one-way carry output signal; the sum logic gate is used for summing two-way sum input signals to obtain a first sum value, and obtaining one-way sum output signal according to the size of the first sum value. By introducing the carry logic gate and the sum logic gate required for carry calculation, the maximum delay path length of the circuit is reduced, the power delay product of the compression unit is reduced, and the circuit performance is improved.
Owner:HUAWEI TECH CO LTD