One-bit full-adder based on FinFET transistors

Abstract

The invention discloses a one-bit full-adder based on FinFET transistors. The one-bit full-adder comprises a first FinFET transistor, a second FinFET transistor, a third FinFET transistor, a fourth FinFET transistor, a fifth FinFET transistor, a sixth FinFET transistor, a seventh FinFET transistor, an eighth FinFET transistor, a ninth FinFET transistor, a tenth FinFET transistor, an eleventh FinFET transistor, a twelfth FinFET transistor, a thirteenth FinFET transistor, a first inverter and a second inverter. The first FinFET transistor, the fourth FinFET transistor, the fifth FinFET transistor, the seventh FinFET transistor, the tenth FinFET transistor and the eleventh FinFET transistor are P-type FinFET transistors. The second FinFET transistor, the third FinFET transistor, the sixth FinFET transistor, the eighth FinFET transistor, the ninth FinFET transistor, the twelfth FinFET transistor and the thirteenth FinFET transistor are N-type FinFET transistors. The one-bit full-adder has an advantage of realizing relatively small area, relatively short time delay, relatively low power consumption and relatively low power delay product on the condition of no circuit performance reduction.

Description

technical field [0001] The invention relates to a one-bit full adder, in particular to a one-bit full adder based on FinFET transistors. Background technique [0002] As the core unit of arithmetic operation, the speed and power consumption of the full adder play a crucial role in the performance of the whole system. For example, in computing circuits such as multipliers, compression trees, comparators, and parity checks, the performance of the full adder, which undertakes the most basic computing functions, obviously affects the overall performance of the computing circuit. In circuit design, low power consumption, small delay and full output swing are the characteristics that the computing unit should have. Only in this way can it provide sufficient driving capability and ensure the stability of the output signal under the condition of low supply voltage. The full adder can be realized with a static gate or a dynamic gate. The advantage of the static gate is that it is st...

AI Technical Summary

Problems solved by technology

Therefore, a commercial EDA tool like DC (Design Compiler) uses an existing process library to design a one-bit full adder circuit such as figure 2 As shown, the one-bit full adder contains more basic gates, and also has the series-parallel problem similar to the traditional static one-bit full adder, namely figure 2 As shown in the dotted line box, the corresponding full adder circuit constructed with FinFET devices may no longer be optimal in terms of circuit performance, namely delay, power consumption and PDP.

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