A pulse d-type flip-flop using floating gate MOS tube

Abstract

The invention discloses a pulse D-type trigger adopting a floating gate MOS (Metal Oxide Semiconductor) pipe. The pulse D-type trigger comprises an inverter chain, two differential configuration pull-down multiple input floating gate MOS pipes, a pair of cross coupling pMOS pipes, and two output inverters, wherein the inverter chain is used for carrying out invert delay on a clock signal, and is formed by cascading three inverters; an on-off state of the two multiple input floating gate MOS pipes is controlled by the clock signal, a delay inversion signal of the clock signal, a data input signal, and an inversion signal of the data input signal, so that the data signal and the inversion signal thereof can be sampled within a narrower pulse width behind an edge of the clock signal; the pair of cross coupling pMOS pipes is used for latching a differential output signal; the two output inverters are used for buffering two complementary output end signals. The pulse D-type trigger has the beneficial effects that the pulse D-type trigger is simpler in structure, smaller in the number of adopted pipes, and better in speed and power consumption. In addition, since the number of the pipes connected into a traditional pull-down MOS pipe cascade network in series is reduced, the pulse D-type trigger can work under lower power voltage.

Description

technical field [0001] The invention relates to a pulse D-type flip-flop, more specifically, it relates to a pulse D-type flip-flop using a floating gate MOS tube. Background technique [0002] Flip-flops are the basic timing modules of digital systems, which have an important impact on the speed, power consumption, area and reliability of digital systems. Among many flip-flop structures, the flip-flop with differential structure has the characteristics of providing complementary dual-rail output at the same time, low power consumption and simple structure, etc., and has been valued. The edge trigger of the differential structure can adopt a master-slave design scheme or a pulse design scheme. The former consists of two stages of differential latches, while the latter consists of only a single latch. The pulse flip-flop drives the latch by generating a short pulse near the rising (falling) edge of the clock to sample the input data, which means that the input data can arri...

AI Technical Summary

Problems solved by technology

However, this flip-flop adopts a master-slave design scheme, which consists of two differential latches using multi-input floating gate MOS transistors, so the performance such as speed and power consumption is not as good as similar pulse flip-flops

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