A controllable diode bootstrap adiabatic circuit and four-stage inverter/buffer

An adiabatic circuit and diode technology, applied in logic circuits, pulse technology, electrical components, etc., can solve the problems of increasing circuit instability, large delay, and large non-adiabatic power consumption, and achieve lower power consumption and lower delay. , the effect of simple circuit structure

Active Publication Date: 2019-02-05
NINGBO UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In the adiabatic ECRL structure adiabatic circuit, due to the existence of the threshold voltage of the MOS transistor, the energy cannot be fully released or recovered in the pre-charging stage and the energy recovery stage. In addition, because its output terminal is suspended, it causes additional power consumption of the circuit. Increased circuit instability
And for the ECRL structure adiabatic circuit, the greater the load, the greater the non-adiabatic power consumption, and the delay is relatively large

Method used

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  • A controllable diode bootstrap adiabatic circuit and four-stage inverter/buffer
  • A controllable diode bootstrap adiabatic circuit and four-stage inverter/buffer
  • A controllable diode bootstrap adiabatic circuit and four-stage inverter/buffer

Examples

Experimental program
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Effect test

Embodiment 1

[0022] Embodiment 1: As shown in Figure 4(a) and Figure 4(b), a controllable diode bootstrap adiabatic circuit includes a first PMOS transistor P1, a second PMOS transistor P2, a first NMOS transistor N1, a second NMOS transistor N2, third NMOS transistor N3, fourth NMOS transistor N4, fifth NMOS transistor N5 and sixth NMOS transistor N6; the source of the first PMOS transistor P1, the source of the second PMOS transistor P2, the third NMOS transistor The drain of N3, the drain of the fourth NMOS transistor N4, the drain of the fifth NMOS transistor N5 and the drain of the sixth NMOS transistor N6 are connected, and the connection end is the clock end of the controllable diode bootstrap adiabatic circuit; the first The gate of the PMOS transistor P1, the drain of the second PMOS transistor P2, the source of the fourth NMOS transistor N4, the drain of the second NMOS transistor N2 and the gate of the sixth NMOS transistor N6 are connected, and the connection terminal is control...

Embodiment 2

[0023] Embodiment 2: As shown in Figure 4(a) and Figure 4(b), a controllable diode bootstrap adiabatic circuit includes a first PMOS transistor P1, a second PMOS transistor P2, a first NMOS transistor N1, a second NMOS transistor N2, third NMOS transistor N3, fourth NMOS transistor N4, fifth NMOS transistor N5 and sixth NMOS transistor N6; the source of the first PMOS transistor P1, the source of the second PMOS transistor P2, the third NMOS transistor The drain of N3, the drain of the fourth NMOS transistor N4, the drain of the fifth NMOS transistor N5 and the drain of the sixth NMOS transistor N6 are connected, and the connection end is the clock end of the controllable diode bootstrap adiabatic circuit; the first The gate of the PMOS transistor P1, the drain of the second PMOS transistor P2, the source of the fourth NMOS transistor N4, the drain of the second NMOS transistor N2 and the gate of the sixth NMOS transistor N6 are connected, and the connection terminal is control...

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PUM

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Abstract

The invention discloses a controllable diode bootstrap adiabatic circuit and a four-level inverter / buffer. The controllable diode bootstrap adiabatic circuit comprises a first PMOS tube, a second PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, and a sixth NMOS tube. The four-level inverter / buffer comprises four controllable diode bootstrap adiabatic circuits. The advantages are as follows: a smaller number of MOS tubes are used, the circuit structure is simple, and the time delay and power consumption are reduced; and the fifth NMOS tube and the sixth NMOS tube constitute a controllable diode feedback path between the output end and the clock end of the controllable diode bootstrap adiabatic circuit, so that energy can be fully recycled, and the time delay, power consumption and power-delay product are smaller on the basis that the circuit performance is not affected.

Description

technical field [0001] The invention relates to an adiabatic circuit, in particular to a controllable diode bootstrap adiabatic circuit and a four-stage inverter / buffer. Background technique [0002] The adiabatic circuit is a dual-rail input, dual-rail output structure circuit, which breaks the traditional energy transmission mode and converts from the original power supply-output node-ground to power supply-output node-power supply. The adiabatic circuit adopts an alternating power supply drive circuit, and the output node is charged by the alternating power supply to complete the assignment, and the energy recovery is realized by recycling the node charge to the power supply. The circuit diagram of the existing adiabatic ECRL structure adiabatic circuit is shown in Fig. 1(a), and its symbol diagram is shown in Fig. 1(b). The structure of the four-stage inverter / buffer designed with this adiabatic ECRL structure Figure such as figure 2 As shown, the waveform diagram of t...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03K19/0944
CPCH03K19/0944
Inventor 胡建平余峰
Owner NINGBO UNIV
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