An adiabatic pal-2n jk flip-flop based on finfet device

Abstract

The invention discloses an adiabatic PAL-2N structure type JK flip-flop based on Fin-FET devices, comprising a first P-type Fin-FET, a second P-type Fin-FET, a third P-type Fin-FET, a fourth P-type Fin-FET, a first N-type Fin-FET, a second N-type Fin-FET, a third N-type Fin-FET, a fourth N-type Fin-FET, a fifth N-type Fin-FET, a sixth N-type Fin-FET, a seventh N-type Fin-FET, an eighth N-type Fin-FET, a ninth N-type Fin-FET, a tenth N-type Fin-FET and an eleventh N-type Fin-FET. The advantage is that under the condition that the circuit performance of the adiabatic PAL-2N structure type JK flip-flop is not affected, the number of Fin-FETs is reduced, the circuit area is reduced significantly, and the time delay, power consumption and power-delay product are reduced significantly.

Description

technical field [0001] The invention relates to a JK flip-flop based on a FinFET device, in particular to an adiabatic PAL-2N structure type JK flip-flop based on a FinFET device. Background technique [0002] The JK flip-flop is an indispensable basic sequential circuit in the digital circuit system, and has an important position in the digital circuit system. The adiabatic ECRL circuit adopts the differential structure of double input and double output. The existing JK flip-flop with better performance is usually realized by the ECRL circuit structure. At present, we call the JK flip-flop realized by the adiabatic ECRL circuit structure as the adiabatic ECRL structure type JK trigger. [0003] With the continuous advancement of VISL technology, the operating speed of digital circuit systems is constantly increasing, and the requirements for the speed of JK flip-flops are also getting higher and higher. FinFET tube (Fin Field-Effect Transistor, Fin Field-Effect Transistor...

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Problems solved by technology

[0004] However, the existing JK flip-flop based on the adiabatic ECRL structure of FinFET devices has the following problems: the existing JK flip-flop based on the adiabatic ECRL structure of FinFET devices uses 22 FinFET tubes to realize the JK flip-flop function, and the number of FinFET tubes is large. Moreover, due to the existence of the threshold voltage of the P-type FinFET tube contained in it, the energy cannot be fully released or recovered in the pre-charging stage and the evaluation stage, and part of the energy is consumed in the resistance, which is lost in the form of heat energy, and its output The node suspension will cause a certain energy loss, which leads to the existing FinFET-based adiabatic ECRL structure type JK flip-flop circuit area, delay, power consumption and power consumption delay product are large

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