Low-power-consumption constant conduction time timing circuit design method and timing circuit

Abstract

The invention provides a low-power-consumption constant conduction time timing circuit design method and timing circuit. An RC circuit is adopted for timing and the static power consumption of the timer is eliminated. The concrete structure is that the timing circuit comprises a fourth PMOS transistor M4 of which the source electrode is connected with input voltage VIN, the gate electrode is connected with the conduction time control end TON_CONTROL and the drain electrode is connected with one end of a fourth resistor R4. The other end of the fourth resistor R4 is connected with one end of afourth capacitor C4. The other end of the fourth capacitor C4 is grounded. The input negative electrode of a comparator VCMP is connected with reference voltage, and the input positive electrode is connected between the fourth capacitor C4 and the fourth resistor R4. According to the circuit under the design method, the static power consumption of the constant conduction time timing circuit can beeliminated so that the power consumption of the whole circuit can be reduced, and the circuit structure is simple and the cost is low.

Description

technical field [0001] The invention relates to the field of electronic circuits, in particular to a design method of a low power consumption constant on-time timing circuit and a timing circuit. Background technique [0002] There are two main types of power chips on the market according to the modulation method: PWM (Pulse Width Modulation), PFM (Pulse Frequency Modulation) and PWM-PFM (Pulse Width Frequency Modulation). Both modulation methods have advantages and disadvantages: [0003] For PWM, the advantages are: 1: low noise, fixed switching frequency, easy design of EMI noise filter; 2: small ripple voltage; 3: easy control method. The disadvantages are: 1. Low light load efficiency; 2. Limited by EA, the loop response speed is slow. [0004] For PFM, there are COT, CFT and hysteresis voltage types. The advantages are: 1: high light load efficiency; 2: small static power consumption; 3: fast loop response. The disadvantages are: 1. The output ripple is larger; 2. T...

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Problems solved by technology

The disadvantages are: 1. Low light load efficiency; 2. Limited by EA, the loop response speed is slow

The disadvantages are: 1. The output ripple is larger; 2. The EMI harmonic spectrum is too wide, and it is difficult to filter

[0008] From Equation 2, it can be obtained that the operating frequency is constant, but for low-power BUCK, figure 1 The disadvantage shown in is that the static power consumption of the EA is relatively large, which makes the need for low-power timers appear

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