An adiabatic ecrl structure type jk flip-flop based on finfet device

A structural and flip-flop technology, applied in the direction of electrical components, pulse technology, pulse generation, etc., can solve the problems of energy loss, loss, circuit area, delay, power consumption and large power consumption delay product, etc., to achieve reduction Effect of energy loss, good charging or recycling

Active Publication Date: 2018-10-09
NINGBO UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, the existing JK flip-flop based on the adiabatic ECRL structure of FinFET devices has the following problems: the existing JK flip-flop based on the adiabatic ECRL structure of FinFET devices uses 22 FinFET tubes to realize the JK flip-flop function, and the number of FinFET tubes is large. And the energy release and recovery of the P-type FinFET tube due to the existence of the threshold voltage, so that the energy can not be fully released or recovered in the pre-charging stage and the evaluation stage, part of the energy is consumed in the resistance, which is lost in the form of heat energy, and its output node Suspension will cause a certain energy loss, which leads to the large circuit area, delay, power consumption and power consumption delay product of the existing JK flip-flop based on FinFET device adiabatic ECRL structure

Method used

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  • An adiabatic ecrl structure type jk flip-flop based on finfet device
  • An adiabatic ecrl structure type jk flip-flop based on finfet device
  • An adiabatic ecrl structure type jk flip-flop based on finfet device

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Embodiment 1

[0023] Embodiment one: if Figure 4As shown, a JK flip-flop based on the adiabatic ECRL structure of FinFET devices includes a first P-type FinFET tube P1, a second P-type FinFET tube P2, a first N-type FinFET tube N1, a second N-type FinFET tube N2, and a second N-type FinFET tube N2. The third N-type FinFET tube N3, the fourth N-type FinFET tube N4, the fifth N-type FinFET tube N5, the sixth N-type FinFET tube N6, the seventh N-type FinFET tube N7, the eighth N-type FinFET tube N8, the ninth N-type tube Type FinFET tube N9, the tenth N-type FinFET tube N10, the eleventh N-type FinFET tube N11, the twelfth N-type FinFET tube N12, and the thirteenth N-type FinFET tube N13; the source of the first P-type FinFET tube P1 , the source of the second P-type FinFET transistor P2, the source electrode of the sixth N-type FinFET transistor N6, and the source electrode of the seventh N-type FinFET transistor N7 are connected, and the connection end is the first power of the adiabatic EC...

Embodiment 2

[0025] Embodiment two: if Figure 4 As shown, a JK flip-flop based on the adiabatic ECRL structure of FinFET devices includes a first P-type FinFET tube P1, a second P-type FinFET tube P2, a first N-type FinFET tube N1, a second N-type FinFET tube N2, and a second N-type FinFET tube N2. The third N-type FinFET tube N3, the fourth N-type FinFET tube N4, the fifth N-type FinFET tube N5, the sixth N-type FinFET tube N6, the seventh N-type FinFET tube N7, the eighth N-type FinFET tube N8, the ninth N-type tube Type FinFET tube N9, the tenth N-type FinFET tube N10, the eleventh N-type FinFET tube N11, the twelfth N-type FinFET tube N12, and the thirteenth N-type FinFET tube N13; the source of the first P-type FinFET tube P1 , the source of the second P-type FinFET transistor P2, the source electrode of the sixth N-type FinFET transistor N6, and the source electrode of the seventh N-type FinFET transistor N7 are connected, and the connection end is the first power of the adiabatic E...

Embodiment 3

[0028] Embodiment three: as Figure 4 As shown, a JK flip-flop based on the adiabatic ECRL structure of FinFET devices includes a first P-type FinFET tube P1, a second P-type FinFET tube P2, a first N-type FinFET tube N1, a second N-type FinFET tube N2, and a second N-type FinFET tube N2. The third N-type FinFET tube N3, the fourth N-type FinFET tube N4, the fifth N-type FinFET tube N5, the sixth N-type FinFET tube N6, the seventh N-type FinFET tube N7, the eighth N-type FinFET tube N8, the ninth N-type tube Type FinFET tube N9, the tenth N-type FinFET tube N10, the eleventh N-type FinFET tube N11, the twelfth N-type FinFET tube N12, and the thirteenth N-type FinFET tube N13; the source of the first P-type FinFET tube P1 , the source of the second P-type FinFET transistor P2, the source electrode of the sixth N-type FinFET transistor N6, and the source electrode of the seventh N-type FinFET transistor N7 are connected, and the connection end is the first power of the adiabatic...

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Abstract

The invention discloses a thermally-insulated ECRL structural JK trigger based on Fin FET devices. The thermally-insulated ECRL structural JK trigger comprises a first P-type Fin FET, a second P-type Fin FET, and first to thirteenth N-type Fin FETs. While not influencing circuit performance, the thermally-insulated ECRL structural JK trigger is decreased in the number of the Fin FETs and is significantly reduced iin circuit area, time delay, power consumption and power consumption time delay product.

Description

technical field [0001] The invention relates to an adiabatic ECRL structure type JK flip-flop, in particular to an adiabatic ECRL structure type JK flip-flop based on a FinFET device. Background technique [0002] JK flip-flop is an indispensable basic sequential circuit in digital circuit system. The adiabatic ECRL circuit adopts a differential structure with two inputs and two outputs. At present, we refer to the JK flip-flop realized by using the adiabatic ECRL circuit structure as the adiabatic ECRL structure type JK flip-flop. [0003] With the continuous advancement of VISL technology, the operating speed of digital circuit systems is constantly increasing, and the requirements for the speed of JK flip-flops are also getting higher and higher. FinFET tube (Fin Field-Effect Transistor, Fin Field-Effect Transistor) is a complementary metal oxide semiconductor (CMOS) transistor, which has the advantages of high speed, low power consumption and small area, and has been us...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03K3/012
CPCH03K3/012
Inventor 胡建平余峰
Owner NINGBO UNIV
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