Integrated Fan-Out Structure with Openings in Buffer Layer

[0033] The manufacture and use of embodiments of the present disclosure are discussed in detail below. However, it should be understood that the embodiments provide many applicable concepts that can be embodied under various specific conditions. The specific embodiments discussed are illustrative and are not intended to limit the scope of the present disclosure.

[0034] According to various exemplary embodiments, an integrated fan-out (InFO) package including through holes and a method of forming the same are provided. The intermediate stages of forming the InFO package are shown. The variation of the embodiment is discussed. In the various figures and shown embodiments, similar reference numerals are used to indicate similar elements.

[0035] Figure 1 to Figure 12 , Figure 13A , Figure 14A , Figure 15 with Figure 16 It is a cross-sectional view of an intermediate stage of manufacturing a package structure according to some exemplary embodiments. Reference figure 1 , The carrier 20 is disposed, and the adhesive layer 22 is disposed on the carrier 20. The carrier 20 may be a blank glass carrier, a blank ceramic carrier, or the like. The adhesive layer 22 may be formed of an adhesive such as ultraviolet (UV) gel, light-to-heat conversion (LTHC) gel, etc., although other types of adhesives may also be used.

[0036] Reference figure 2 , The buffer layer 24 is formed on the adhesive layer 22. The buffer layer 24 is a dielectric layer, which may be a polymer layer including a polymer. The polymer may be, for example, polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), Ajinomoto reinforced film (ABF), solder mask (SR), and the like. The buffer layer 24 is a flat layer having a uniform thickness, where the thickness T1 may be greater than about 2 μm, and may be between about 2 μm and about 40 μm. The top and bottom surfaces of the buffer layer 24 are also flat.

[0037] For example, by physical vapor deposition (PVD) or metal foil lamination, the seed layer 26 is formed on the buffer layer 24. The seed layer 26 may include copper, copper alloy, aluminum, titanium, titanium alloy, or a combination thereof. In some embodiments, the seed layer 26 includes a titanium layer 26A and a copper layer 26B located above the titanium layer 26A. In an alternative embodiment, the seed layer 26 is a copper layer.

[0038] Reference image 3 , The photoresist 28 is coated on the seed layer 26 and then patterned. As a result, an opening 30 is formed in the photoresist 28, and some parts of the seed layer 26 are exposed through the opening.

[0039] Such as Figure 4 As shown, the metal features 32 are formed in the photoresist 28 by plating (which may be electroplating or electroless plating). The metal part 32 is plated on the exposed portion of the seed layer 26. The metal component 32 includes copper, aluminum, tungsten, nickel, solder, or their alloys. The top view shape of the metal component 32 may be rectangular, square, circular, or the like. Pass the subsequently placed die 34 ( Figure 7 ) To determine the height of the metal component 32. In some embodiments, the height of the metal component 32 is greater than the thickness of the die 34. After the metal part 32 is plated, the photoresist 28 is removed, and the Figure 5 The resulting structure is shown in. After the photoresist 28 is removed, the part of the seed layer 26 covered by the photoresist 28 is exposed.

[0040] Reference Image 6 An etching step is performed to remove the exposed portion of the seed layer 26, where the etching may be anisotropic etching. On the other hand, the portion of the seed layer 26 overlapping with the metal member 32 remains unetched. Throughout the description, the metal part 32 and the remaining lower portion of the seed layer 26 are collectively referred to as an InFO via (TIV) 33, which is also referred to as a via 33. Although the seed layer 26 is shown as a separate layer from the metal member 32, when the seed layer 26 is formed of a material similar to or the same as the corresponding upper metal member 32, the seed layer 26 may be combined with the metal member 32 to form There is no discernible interface between them. In an alternative embodiment, there may be a discernible interface between the seed layer 26 and the metal component 32.

[0041] Figure 7 The placement of the device die 34 above the buffer layer 24 is shown. The device die 34 may be bonded to the buffer layer 24 through the adhesive layer 36. The device die 34 may be a logic device die including logic transistors. In some exemplary embodiments, the device die 34 is designed for mobile applications, and may be a central computing unit (CPU) die, a power management integrated circuit (PMIC) die, a transceiver (TRX) die, and the like. Each device die 34 includes a semiconductor substrate 35 (for example, a silicon substrate) in contact with the adhesive layer 36, wherein the backside of the semiconductor substrate 35 is in contact with the adhesive layer 36.

[0042] In some exemplary embodiments, a metal pillar 40 (such as a copper pillar) is formed on top of the device die 34 and is electrically connected to a device such as a transistor (not shown) in the device die 34. In some embodiments, the dielectric layer 38 is formed on the top surface of the corresponding device die 34, and the lower part of the metal pillar 40 is located at least in the dielectric layer 38. In some embodiments, the top surface of the metal pillar 40 may also be flush with the top surface of the metal pillar 40. Optionally, the dielectric layer 38 is not formed, and the metal pillar 40 protrudes above the top dielectric layer of the corresponding device die 34.

[0043] Reference Picture 8 , The molding material 42 is molded on the device die 34 and the TIV33. The molding material 42 fills the gap between the device die 34 and the TIV 33 and may be in contact with the buffer layer 24. In addition, when the metal pillars 40 are protruding metal pillars, the molding material 42 is filled into the gaps between the metal pillars 40. The molding material 42 may include molding compound, molded underfill, epoxy, or resin. The top surface of the molding material 42 is higher than the top of the metal pillar 40 and the TIV33.

[0044] Next, a grinding step is performed to thin the molding material 42 until the underfill metal pillar 40 and the TIV 33 are exposed. in Picture 9 The resulting structure is shown in. Due to the grinding, the top end 32A of the metal part 32 is substantially flush (coplanar) with the top end 40A of the metal post 40 and substantially flush (coplanar) with the top surface 42A of the molding material 42. As a result of grinding, metal residues such as metal particles may be generated and left on the top surfaces 32A, 40A, and 42A. Therefore, after grinding, cleaning may be performed, for example, by wet etching, so that metal residues are removed.

[0045] Next, refer to Picture 10 , A redistribution line (RLD) 44 is formed over the molding material 42 to connect to the metal pillar 40 and the TIV33. The RDL44 can also interconnect the metal pillar 40 and the TIV33. According to various embodiments, one or more dielectric layers 46 are formed on Picture 9 Above the structure shown, where RDL44 is formed in the dielectric layer 46. In some embodiments, the formation of one of the RDL 44 and the dielectric layer 46 includes: forming a blanket copper seed layer; forming and patterning a mask layer over the blanket copper seed layer; performing plating to form the RDL 44; Remove the mask layer; and perform quick execution to remove the parts of the blanket copper seed layer that are not covered by RDL44. In an alternative embodiment, the RDL 44 is formed by the following methods: depositing a metal layer; patterning the metal layer; and filling the gap between the RDL 44 with a dielectric material 46. RDL44 may include metals or metal alloys, including aluminum, copper, tungsten, and/or their alloys. Picture 10 Two layers of RDL44 are shown, although there may be one layer or more than two layers of RDL depending on the wiring requirements of the corresponding package. In these embodiments, the dielectric layer 46 may include polymers such as polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), and the like. Optionally, the dielectric layer 46 may include a non-organic dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, and the like.

[0046] Picture 11 The formation of electrical connections 48 according to some exemplary embodiments is shown. The formation of the electrical connector 48 may include: placing solder balls (or bottom bump metal (if formed, not shown)) on the exposed portion of the RDL 44, and then reflowing the solder balls. In an alternative embodiment, the electrical connector 48 The formation includes: performing a plating step to form a solder area above the RDL 44, and then reflowing the solder area. The electrical connection 48 may also include a metal pillar or a metal pillar and a solder cap, which may be formed by a plating process. In the entire description, including The combined structure of the device die 34, the TIV 33, the molding material 42, the overlying RDL 44, the dielectric layer 46, and the buffer layer 24 is called a TIV package 50, which may be a combined wafer.

[0047] Next, the TIV package 50 is separated from the carrier 20. The adhesive layer 22 is also cleaned from the TIV package 50. in Picture 12 The resulting structure is shown in. As a result of removing the adhesive layer 22, the buffer layer 24 is exposed. The TIV package 50 is further bonded to the dicing tape 52, wherein the electrical connection member 48 faces the dicing tape 52 and can contact the dicing tape 52. In some embodiments, the laminate film 54 is placed on the exposed buffer layer 24, where the laminate film 54 may include SR, ABF, backside coating tape, and the like. Among the optional films, no laminate film 54 is placed on the buffer layer 24.

[0048] Figure 13A The openings of the buffer layer 24 and the laminate film 54 (if any) are shown. The opening 56 and the guide groove 58 are formed in the buffer layer 24 and the laminate film 54. According to some embodiments, laser drilling is used to form the opening 56 and the guide trench 58, although a photolithography process can also be used. The TIV 33 is exposed through the opening 56. In the seed layer 26 ( figure 1 ) In an embodiment including the titanium portion 26A, an etching step is performed to remove the titanium portion 26A, so that the copper portion 26B of the seed layer 26 is exposed. Otherwise, if the seed layer 26 does not include titanium, the etching step is skipped.

[0049] Figure 13B to Figure 13D Shows the topography of opening 56 when laser drilling is used to form opening 56, and Figure 13E to Figure 13J An exemplary opening 56 of variable size is shown. Figure 13B A cross-sectional view showing a portion of the opening 56 in the laminate film 54 and the buffer layer 24 (for example, in the corresponding Figure 13A In the X-Z plane of the cross-sectional view). As a result of the laser drilling 82 forming the opening 56, the buffer layer 24 may have corrugations 80. Laser drilling 82 (e.g., laser) may be impinged on each layer at an incident angle θ relative to the normal 84 of those layers (e.g., in the Z direction shown). As shown in the figure, the corrugations 80 are formed in the buffer layer 24, while in other embodiments, the corrugations 80 may also be formed in the laminate film 54 (if present). As shown in the figure, the corrugations 80 in the buffer layer 24 are away from the sidewall of the laminated film 54 and project toward the opening 56.

[0050] Figure 13C with Figure 13D The layout of the opening 56 is shown (for example in the X-Y plane). Figure 13D Shows in further detail Figure 13C In the diagram 86. The corrugations 80 in the buffer layer 24 are formed around the opening 56. The corrugations 80 may be periodically arranged around the opening 56. The opening 56 may have a diameter D, which may be the diameter of the portion of the seed layer 26 and/or the TIV 33 exposed by the opening 56. The diameter D can be represented by an instantaneous diameter (which can be from corrugation 80 to relative corrugation 80, from wave trough to relative wave trough, or from wave trough to relative corrugation 80). Average diameter D AVE It can be expressed as the average value of the instantaneous diameter D across the opening 56. In some embodiments, the average diameter DAVE of the opening 56 may be from about 10 μm to about 600 μm.

[0051] Adjacent corrugations 80 may have a peak-to-peak distance Δ. In addition, the corrugations 80 may have a valley-peak height H. In some embodiments, the height H of the corrugations 80 may be from about 0.2 μm to about 20 μm. In some embodiments, the distance Δ may be from about 0.2 μm to about 20 μm. In some embodiments, the distance Δ can be expressed as Where λ is the wavelength of the radiation used in laser drilling (for example, laser), and θ is the incident angle of the radiation used in laser drilling (for example, Figure 13B Shown). In some embodiments, the laser source used for laser drilling may be a UV source (which may have a wavelength of 355nm), a green source (which may have a wavelength of 532nm), a Nd:YAG source (which may have a wavelength of 1064nm), CO 2 Source (which can have a wavelength of 9.4 μm), etc. in Figure 13C with Figure 13D In the illustrated embodiment of, the height H is approximately 8 μm, and the distance Δ is approximately 10 μm.

[0052] Figure 13E to Figure 13J Shows different average diameters D AVE The layout of the opening 56 (for example, in the X-Y plane). Figure 13E The average diameter of the opening 56 in D AVE It is 80μm. Figure 13F The average diameter of the opening 56 in D AVE It is 120μm. Figure 13G The average diameter of the opening 56 in D AVE It is 152μm. Figure 13H The average diameter of the opening 56 in D AVE It is 190μm. Figure 13I The average diameter of the opening 56 in D AVE It is 220μm. Figure 13J The average diameter of the opening 56 in D AVE It is 250μm.

[0053] Back to reference Figure 13A , A guide groove 58 is also formed in the buffer layer 24 and the laminated film 54. In some embodiments, such as Figure 14B As shown, the guide groove is formed in a ring shape. Therefore, the guide groove 58 is optionally referred to as a guide groove ring 58, although it may also be formed as a separate guide groove belt or a partial ring shape. As shown in FIG. 13, in some embodiments, each guide groove 58 may surround the central portion of the buffer layer 24 overlapping the entire device die 34, wherein the guide groove 58 is not aligned with the device die 34. In other words, the guide trench 58 does not extend into the area directly overlying the device die 34. The bottom of the guiding groove 58 may be substantially flush with the top surface 42A of the molding material 42 so that the guiding process 58 passes through the buffer layer 24 and the laminated film 54. In an alternative embodiment, the guide groove 58 does not pass through the buffer layer 24 and the lower portion of the buffer layer 24 remains under the guide groove 58. In yet another alternative embodiment, the guide groove 58 passes through the buffer layer 24 and extends into the molding material 42.

[0054] Next, the TIV package 50 is cut into a plurality of TIV packages 60. Figure 14A with Figure 14B A cross-sectional view and a top view of a TIV package 60 are shown respectively. In some embodiments, solder paste (not shown) is applied to protect the exposed TIV33. In an alternative embodiment, no solder paste is applied. Such as Figure 14B As shown, in the top view, the guide groove ring 58 surrounds the device die 34. Although the inner edge of the guide groove ring 58 is shown as offset from the corresponding edge of the device die 34, the inner edge of the guide groove ring 58 may also be aligned with the edge of the corresponding device die 34. In some embodiments, there is a single guide groove ring 58 in each TIV package 60. In alternative embodiments, there are two or more guide groove rings 58. The widths W1 and W2 of the guide groove ring 58 may be greater than about 60 μm, and may be between about 60 μm and about 250 μm. The depth D1 ( Figure 14A ) May be greater than about 2 μm, and may be between about 2 μm and about 50 μm.

[0055] Figure 15 The bonding of the top package 62 and the TIV package 60 is shown, where the bonding can be achieved through the solder area 68. Throughout the description, the TIV package 60 is also referred to as the bottom package 60 because of Figure 15 They are shown as bottom packages. In some embodiments, the top package 62 includes a device die 66 bonded to the package substrate 64. The device die 66 may include a storage die, which may be, for example, a static random access memory (SRAM) die, a dynamic random access memory (DRAM) die, or the like. The bottom surface of the top package 62 and the top surface of the TIV package 60 are separated from each other by a gap 70, wherein the top package 62 and the TIV package 60 may have a separation distance S1, which may be between about 10 μm and about 100 μm, although they are separated The distance S1 can also have other values.

[0056] Reference Figure 16 After the bonding, the top package 62 and the TIV package 60 are further bonded to another package component 72 (in some embodiments, it may be a package substrate). In an alternative embodiment, the package component 72 includes a printed circuit board (PCB). The package component 72 may have electrical connectors 76 (such as metal pads or metal pillars) on opposite sides thereof, and metal wires 78 interconnect the electrical connectors 76.

[0057] In some embodiments, the underfill 74 is dispensed to fill the gap 70 ( Figure 15 ). The underfill 74 can also seal the peripheral portion of the gap 70, and the central portion 70' of the gap 70 is not filled with the underfill 74. During the distribution of the underfill 74, the underfill 74 flows into the gap 70 and the guide groove 58 ( Figure 15 ). Since the guide groove 58 is deeper than the central portion 70' of the gap 70, the underfill 74 flows faster in the guide groove 58 than in the central gap portion 70'. Therefore, the underfill 74 will first fill the guide trench 58 before it can flow into the central portion 70' (overlapped with the device die 34). By ending the underfill process at an appropriate time, the underfill 74 is filled into the guide trench 58 but does not enter the central gap portion 70'. Therefore, the underfill 74 can surround but not fill the central gap portion 70'. Therefore, the central gap portion 70' is maintained as a blank space, which may be a gas gap filled with gas or a vacuum space.

[0058] In the embodiment of the present invention, the TIV package and the overlying top package are separated from each other by a blank space, where the blank space may be a gas gap or a vacuum space. Since the thermal insulation capability of the empty space is better than that of the underfill, the empty space has better ability to prevent the heat of the device die in the TIV package from being conducted to the die in the top package and affecting the tube in the top package. Operation of the core. It should be understood that if the guide groove is not formed, the distance that the underfill fills into the gap between the TIV package and the top package is random, so the formation of the empty space will be uneven. By forming guide grooves in the buffer layer, the formation of empty spaces is more controllable and more uniform.

[0059] According to some embodiments, a bottom package includes a molding compound, a buffer layer above and in contact with the molding compound, and a through hole through the molding compound. The device die is molded in the molding compound. The guide groove extends from the top surface of the buffer layer into the buffer layer, wherein the guide groove is not aligned with the device die.

[0060] According to other embodiments, a package includes a bottom package and a top package joined to the bottom package. The bottom package includes: a molding compound with a flat top surface and a flat ground; a device die, molded in the molding compound; a flat dielectric layer, located above the flat top surface of the molding compound and contacting the flat top surface of the molding compound; A hole through the molding compound; and a first guide groove ring located in the flat dielectric layer. The top package and the bottom package are separated by a gap, wherein the first guide groove ring is connected to the gap. The underfill fills the periphery of the gap and at least a part of the first guide groove ring, wherein a central part of the gap is surrounded by the underfill, and the central part forms a blank space.

[0061] According to still other embodiments, a method includes: forming a through hole above a dielectric buffer layer; placing a device die above the dielectric buffer layer; molding the device die and the through hole in a molding compound; and a planarization mold Plastic to expose the through holes and metal pillars of the device die. The redistribution line is formed overlying the through hole and the metal pillar and is electrically connected to the through hole and the metal pillar. An opening is formed in the dielectric buffer layer to expose the through hole. A guide groove ring is formed in the dielectric buffer layer.

[0062] According to still other embodiments, a structure includes a first package. The first package includes a molding compound, a through hole passing through the molding compound, a device die molded in the molding compound, and a buffer layer on the molding compound and contacting the molding compound. The opening passes through the buffer layer to the through hole. The buffer layer has corrugations that are in a plane parallel to the interface between the molding compound and the buffer layer and surround the opening.

[0063] According to still other embodiments, a structure includes a first package and a second package joined to the first package. The first package includes: a molding compound including a flat top surface and a flat bottom surface; a device die, which is laterally sealed by the molding compound; a through hole, which passes through the molding compound; and a flat dielectric layer, which is located above the flat top surface of the molding compound And touch the flat top surface of the molding compound. The opening passes through the flat dielectric layer to the through hole. The flat dielectric layer has corrugations around the opening. The external electrical connector electrically couples the first package to the second package, and the external electrical connector is at least partially disposed in the opening.

[0064] According to still other embodiments, a method includes forming a package. Forming the package includes forming a composite structure. The combined structure includes device die, molding compound, and through holes. The molding compound at least partially seals the device die between the first surface of the molding compound and the second surface of the molding compound. The through hole is in the molding compound and extends from the first surface of the molding compound to the second surface of the molding compound. Forming the package further includes: forming a buffer layer on the first surface of the molding compound; and using laser drilling to form an opening to the through hole through the buffer layer. The buffer layer has corrugations around the opening.

[0065] Although the embodiments and their advantages have been described in detail, it should be understood that various modifications, substitutions and changes can be made without departing from the spirit and scope defined by the appended claims. In addition, the scope of the present invention is not limited to specific embodiments of processes, machines, manufacturing, and combinations of things, devices, methods, and steps described in the specification. Those skilled in the art can easily understand that, according to the present disclosure, existing or later-developed processes, machines, manufacturing, things, devices, etc. that perform substantially the same functions or achieve substantially the same results as the corresponding embodiments described herein can be utilized. A combination of methods and steps. Therefore, the appended claims are included in these processes, machines, manufacturing, and combinations of things, devices, methods and steps. In addition, each claim constitutes an independent embodiment, and the combination of each claim and embodiment is included in the scope of the present invention.