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System-in-package structure

A system-in-package, chip technology, applied in electrical components, electro-solid devices, circuits, etc., can solve problems such as unfavorable chip power supply consistency, increase the number and length of traces, increase production costs, etc., to reduce power and The effect of grounding trace length, improving consistency, and improving work stability

Inactive Publication Date: 2016-07-20
GIGADEVICE SEMICON (BEIJING) INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This power connection method increases the number and length of wiring, which is not conducive to the consistency of power supply of each chip, and also increases the production cost.

Method used

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Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0043] figure 2 A schematic top view of a system-in-package structure provided in Embodiment 1 of the present invention, as shown in figure 2 As shown, the system-in-package structure includes: a substrate 23 , a first chip 21 , a second chip 22 and electrical connection wires 24 . Wherein, the first chip 21 and the second chip 22 are stacked on the substrate 23, and the power terminal 211 and the ground terminal 212 of the first chip 21 are respectively connected to the power terminal 221 and the ground terminal of the second chip 22 through the electrical connecting wire 24. 222. Moreover, the power terminal 211 and the ground terminal 212 of the first chip 21 below the stack are respectively connected to the external power supply pin 25 and the external ground pin 26 through the electrical connection wire 24 .

[0044] The embodiment of the present invention solves the problem that the power terminals and ground terminals of each chip in the system-level packaging struc...

Embodiment 2

[0048] image 3 A schematic top view of a system-in-package structure provided in Embodiment 2 of the present invention, as shown in image 3 As shown, the system-in-package structure includes: a substrate 33 , a first chip 31 , a second chip 32 and electrical connection wires 24 . Wherein, the first chip 31 and the second chip 32 are tiled on the substrate 33, and the power terminal 311 and the ground terminal 312 of the first chip 31 are respectively connected to the power terminal 321 and the ground terminal of the second chip 32 through the electrical connecting wire 34. 322 , while the power terminal 311 and the ground terminal 312 of the first chip 31 are respectively connected to the external power supply pin 35 and the external ground pin 36 through the electrical connection wire 34 . The power terminal 311 and the ground terminal 312 of the first chip 31 are located on the top surface of the first chip 31 , and the power terminal 321 and the ground terminal 322 of th...

Embodiment 3

[0051] Figure 4 A schematic top view of a system-in-package structure provided by Embodiment 3 of the present invention, as shown in Figure 4 As shown, the system-in-package structure includes: a substrate 44 , a first chip 41 , a second chip 42 , a third chip 43 and electrical connection wires 45 . The first chip 41 and the second chip 42 are tiled and arranged on the substrate 44 together, the third chip 43 is arranged on the first chip 41 to form a laminated structure, and the power terminals 431 of the third chip 43 are respectively connected by electrical connecting wires 45 The power terminal 411 of the first chip 41 and the power terminal 421 of the second chip 42, and the ground terminal 432 of the third chip 43 are respectively connected to the ground terminal 412 of the first chip 41 and the ground terminal of the second chip 42 through the electrical connecting wire 45 422 , and the power terminal 411 and the ground terminal 412 of the first chip 41 are respectiv...

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PUM

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Abstract

The invention discloses a system-in-package structure, which comprises a substrate, at least two chips and electrical connection lines, wherein the at least two chips are tiled and / or laminated on the substrate; each chip comprises a power terminal and a ground terminal; the power terminals of various chips are connected with one another through the electrical connection lines; the power terminal of one chip is connected with an external power supply pin through one electrical connection line; the ground terminals of various chips are connected with one another through the electrical connection lines; and the ground terminal of one chip is connected with an external ground pin through one electrical connection line. According to the system-in-package structure, the power supply consistency of various chips in the system-in-package structure is ensured; the working stability of a system-in-package chip is improved; the lengths of the power traces and ground traces of various chips in the system-in-package structure are reduced; and the production cost is reduced.

Description

technical field [0001] Embodiments of the present invention relate to integrated circuit packaging technologies, and in particular to a system-in-package structure. Background technique [0002] System-in-Package (SystemInPackage, SIP) is to integrate multiple functional chips, including processors, memory and other functional chips into one package, so as to realize a basically complete function. Using the SIP package can have better performance and reduce the size of the electronic system. [0003] figure 1 It is a schematic top view structure diagram of a system-in-package structure in the prior art, such as figure 1 As shown, the system-in-package includes: a first chip 11, a second chip 12, a substrate 13, a power supply pin 14, a ground pin 15 and an electrical connection wire 16, wherein the first power supply terminal 111 of the first chip 11 and the The first ground terminal 112, the second power supply terminal 121 and the second ground terminal 122 of the secon...

Claims

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Application Information

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IPC IPC(8): H01L23/49H01L25/18
CPCH01L25/18H01L23/49H01L2924/19107H01L2224/48137H01L2224/48139H01L2224/48145H01L2224/48147H01L2224/48247
Inventor 苏志强刘会娟钱建琴
Owner GIGADEVICE SEMICON (BEIJING) INC