High efficiency video coding adder tree parallel implementation method

A high-efficiency video coding and implementation method technology, applied in the field of integer pixel motion estimation and high-efficiency video coding, can solve the problems of hardware area increase, etc., and achieve the effect of accelerating calculation speed, improving calculation efficiency, and improving operation efficiency

Active Publication Date: 2016-08-10
XIAN UNIV OF POSTS & TELECOMM
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Problems solved by technology

For HEVC, the maximum coding block size is 64×64 pixels. If the same or similar design architecture is used, 4096 computing units are requir

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  • High efficiency video coding adder tree parallel implementation method
  • High efficiency video coding adder tree parallel implementation method
  • High efficiency video coding adder tree parallel implementation method

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Embodiment Construction

[0048] The principles and features of the present invention are described below in conjunction with the accompanying drawings, and the examples given are only used to explain the present invention, and are not intended to limit the scope of the present invention.

[0049] The following embodiments provide a new and efficient method for implementing an addition tree based on a two-dimensional array processor,

[0050] figure 1 is a schematic diagram of PE adjacency interconnection, and the addition tree is realized on the two-dimensional adjacency interconnection PE array;

[0051] figure 2 It is a schematic diagram of the addition tree array and buffer area distribution. The gray part is the buffer area module (the leftmost column is buffer area 1, the rightmost column is buffer area 2, and the bottom row is buffer area 3), and the middle 16×16 PEs are addition tree module. A total of 18×17 PEs are used;

[0052] Step 1: Read the 64×64 brightness block into the additive tr...

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Abstract

The invention provides a high efficiency video coding (HEVC) adder tree parallel implementation method, and relates to the technical field of digital video coding and decoding. By utilizing a two-dimensional processing element array structure, an SAD value in a luminance block division mode is computed and is subjected to parallel processing, so that motion estimation computation efficiency is effectively improved; and by utilizing a method for selecting a processing element (PE) for storing the SAD value according to the type of the block division mode, computation speed of an adder tree is increased, and computation efficiency is improved. Compared with the traditional pixel block storage manner (storing a single pixel through the single PE ), a manner of storing 4*4 pixel blocks through the single PE has the advantage that the amount of utilized PEs is reduced to 1/16th of the original amount of the utilized PEs; compared with an adder tree serial structure implementation method, the parallel implementation method has the speed increased to nearly 100 times; and computation of the SAD values in twelve types of the block division modes are obtained through combination of the SAD values in 4*4 block division modes, so that excess computation processes can be reduced, and computation efficiency is improved.

Description

technical field [0001] The present invention relates to the technical field of digital video coding and decoding, in particular to an integer pixel motion estimation method in High Efficiency Video Coding (HEVC for short). Background technique [0002] Motion estimation is a widely used technique in video coding and video processing. The basic idea of ​​motion estimation is that each frame in the graphics can be divided into non-overlapping blocks because there is a certain correlation between the scenes in the adjacent frames of the active image, and the displacement of all pixels in the block is considered to be the same. Then try to find out the position of each block in the adjacent frame, and get the relative offset of the two in the space position, the relative offset is usually called the motion vector, the process of obtaining the motion vector is called for motion estimation. [0003] With the continuous improvement of video quality, H.264 can no longer meet the c...

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Application Information

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IPC IPC(8): H04N19/176H04N19/96H04N19/436
CPCH04N19/176H04N19/436H04N19/96
Inventor 崔继兴谢晓燕张阿宁
Owner XIAN UNIV OF POSTS & TELECOMM
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