A kind of preparation method of dram device

Abstract

The present invention relates to the field of semiconductor technology, in particular to a method for preparing a DRAM device provided in this embodiment, which mainly reduces the area of ​​the byte cell region by forming a three-dimensional NMOS device, that is, the semiconductor device that has been prepared in the peripheral region A dielectric layer is deposited on the substrate, and deep holes are formed by etching, and gate oxide layers, polysilicon layers, and sidewalls are prepared in the deep holes to form channels. The selection ratio of the wet process is different to form a gap to fill metals such as tungsten, and then lead out each terminal point in the NMOS to form a three-dimensional NMOS structure, so that the area of ​​the DRAM unit structure is greatly reduced compared with the traditional DRAM. Devices that can achieve a technology node of 0.18 μm and below have longer channels, thereby effectively reducing the off-current Ioff of the device.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for preparing a DRAM device. Background technique [0002] At present, in the integrated manufacturing process of DRAM (Dynamic Random Access Memory, dynamic random access memory structure) devices, in order to improve the performance of the device, it is often necessary to make a larger capacitor per unit area and control the leakage current of the device more effectively. For example, a three-dimensional capacitor unit can be prepared using a three-dimensional structure such as a trench (Trench, TRC) and a stacked (Stacked, STC) to increase the capacitance per unit area; in the current DRAM structure unit (cell), the MOS tube also They are all tiled on the surface of the wafer, and the connection with the three-dimensional capacitor is only realized at the source of the MOS transistor through a method such as TRC or STC. [0003] In addition, in order to minimi...

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Problems solved by technology

[0003] In addition, in order to minimize the area of ​​the DRAM structural unit and the leakage current of the device, it is required that in the NMOS storage array of the DRAM device, the gate length L of the MOS should be as small as possible, the off-current Ioff should be as low as possible, and as much as possible to generate as much power as possible. Low junction field leakage current, and the current technical means are far from meeting the process requirements; especially in the 0.18μm and below node process, due to the existence of STI (Shallow Trench Isolation) process such as Si defects caused by excessive stress , etch defects (such as increased leakage current at the connection point) and angular roundness defects (such as transistor reading leakage current effect), etc., will affect the refresh time of subsequent devices

[0004] At the same time, current methods such as thick gate oxide layer (for example, the thickness of the gate oxide layer (GOX) can be designed to be two generations behind the logic circuit thickness), halo ion implantation (halo implant), control of STI process-related parameters (such as composition Depth, ion implantation angle, substrate oxide temperature and annealing temperature, etc.) to reduce the leakage current of the device, but none of them can achieve the desired effect

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