Semiconductor wafer measuring device and method

Abstract

The invention relates to a measuring apparatus and method for a semiconductor wafer. The measuring apparatus comprises probes, a driving wheel, and a bearing rack. The probes include eddy current probes. The bearing rack consists of a sliding rail and a rotating ring, wherein the shape of the sliding rail matches that of the rotating ring. A wafer for testing is placed on the rotating ring; and the relative positions of the wafer and the rotating ring are limited by the part, in contact with the edge of the wafer, of the rotating ring. The rotating ring drives the wafer to rotate on the sliding rail and no relative sliding occurs between the wafer and the rotating ring during the rotation process; and the rotation of the rotating ring is driven by the driving wheel. The eddy current probes include an emission probe and a receiving probe; the emission probe and the receiving probe are arranged at the front side and the back side of the wafer respectively in a non-contact mode during wafer measurement and point to the plane where the wafer is located vertically in a collineation mode all the time, so that the receiving probe receives an excitation signal generated by the emission probe. In addition, the invention also discloses a method for measuring a wafer by using the measuring apparatus.

Description

technical field [0001] The invention relates to the field of semiconductor processing and testing, in particular to a device and method for measuring semiconductor wafers in a stress-free polishing process. Background technique [0002] With the development of the semiconductor industry, Very Large Scale Integration (VLSI) and Ultra Large Scale Integration (ULSI) have been widely used. Compared with previous integrated circuits, VLSI and VLSI have more complex multi-layer structures and smaller feature sizes. The stress-free planarization technology can overcome the defects of the traditional chemical mechanical planarization technology in ultra-fine feature size integrated circuits. Stress-free polishing technology is based on electrochemical principles and can planarize metal interconnect structures without mechanical stress. The stress-free polishing technology can precisely control the removal rate of the wafer surface in a specific area by controlling the current dens...

AI Technical Summary

Problems solved by technology

However, the receiving (or transmitting) probes on both sides of the wafer are easily interfered by the fixture that fixes the wafer, making it difficult to sample and calculate points on the wafer located in the clamping area. If the fixture design is unreasonable, it will cause greater Points on the wafer with a larger area are shaded, which will seriously affect the accuracy of the measurement

Even if the number of shaded points is small, a special measurement process is still required to avoid these holding structures, adding cumbersome steps and raising process costs

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