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ESD protection circuit

An ESD protection and circuit technology, applied in circuits, electrical components, electrical solid devices, etc., can solve the problems of small circuit area, high ESD trigger voltage, avoid device breakdown, reduce NMOS and PMOS area, and enhance ESD performance. Effect

Inactive Publication Date: 2016-11-09
CHIPSEA TECH SHENZHEN CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] Based on this, the present invention provides an ESD protection circuit, which protects the protected circuit from electrostatic damage caused by external static electricity, solves the ESD protection problem in applications where relative positive and negative potentials occur between nodes, and solves the problem of ESD trigger voltage high problem while having a small circuit area

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Embodiment Construction

[0017] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

[0018] Such as figure 2 As shown, the ESD protection circuit realized by the present invention includes: a resistor R, a capacitor C, a large-size NMOS, and a large-size PMOS. Resistor R and capacitor C form a detection circuit capable of detecting ESD events. Large-size NMOS or large-size PMOS, in the ESD event, is in the conduction state, avoiding device breakdown, the trigger voltage is very low, and the static electricity is released in time and effectively, which greatly enhances the ESD performance of the circuit; compared with conventional methods, To achieve the same ESD level, the requi...

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Abstract

The invention discloses an ESD protection circuit, and the circuit comprises a PMOS tube and an NMOS tube. The PMOS tube is a large-size PMOS tube, and the NMOS tube is also a large-size NMOS tube. The circuit also comprises a detection circuit, and the detection circuit is connected to the large-size PMOS tube and the large-size NMOS tube. The circuit prevents the breakdown of a device through the large-size PMOS tube or the large-size NMOS tube, can release static electricity timely and effectively, greatly improves the ESD performance, and also can provide ESD protection for an application occasion where a relatively positive and negative potential appears between nodes.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits, in particular to an ESD protection circuit for integrated circuits. Background technique [0002] Electrostatic discharge protection (ESD protection) is specially used for electrostatic discharge protection on integrated circuits. This electrostatic discharge protection provides an ESD current discharge circuit to prevent ESD current from flowing into the internal circuit of the IC and causing damage when ESD is discharged. [0003] In some applications, relative positive and negative potentials appear between the power supply and ground of integrated circuits, or between IO ports, or between power supplies and ground wires in multi-power chips. figure 1 ESD protection structure. This structure involves device breakdown and discharge process, the trigger voltage is high, the ESD protection capability is low, and a large area is required. [0004] For example, patent application 2011...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/02
CPCH01L27/0248
Inventor 陆让天
Owner CHIPSEA TECH SHENZHEN CO LTD
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