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Erasing and writing-in circuit and method used for EEPROM (Electrically Erasable Programmable Read-Only Memory)

A technology for writing circuits and memories, applied in static memory, read-only memory, information storage, etc., can solve the problems of low utilization rate of EEPROM storage space, inflexible EEPROM writing data, unusable application occasions, etc., to achieve storage space utilization The effect of high rate, flexible data writing, and fast data writing speed

Inactive Publication Date: 2016-11-23
深圳市航顺芯片技术研发有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] 1. Writing data to EEPROM is inflexible, and cannot be used in some applications
[0004] 2. EEPROM write data must be written in the whole page, and the utilization rate of EEPROM storage space is low
[0005] 3. For applications that only need to update a small amount of data, the speed of writing data is slow

Method used

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  • Erasing and writing-in circuit and method used for EEPROM (Electrically Erasable Programmable Read-Only Memory)
  • Erasing and writing-in circuit and method used for EEPROM (Electrically Erasable Programmable Read-Only Memory)
  • Erasing and writing-in circuit and method used for EEPROM (Electrically Erasable Programmable Read-Only Memory)

Examples

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Embodiment 1

[0028] An erasing and writing circuit for EEPROM memory, comprising: timing control module, storage module, input and output module, page cache module, page address decoder; it is characterized in that, also includes: address decoder in the page , the storage steps are as follows:

[0029] S101, the timing control circuit generates a signal PE after receiving the write signal W;

[0030] S102, the page address decoder decodes and selects the page address to be erased;

[0031] S103, saving the page data to be erased in the page cache;

[0032] S104, the timing control module generates an E signal to erase the page data of the selected page address;

[0033] S105, the byte address decoder in the page decodes and selects the byte address that needs to write data in the page buffer;

[0034] S106, writing the data to be updated into the byte address of the selected page buffer;

[0035] S107, the timing control module generates a W signal, and writes the data in the page buff...

Embodiment 2

[0040] The present invention is used for erasing and writing circuit and method thereof for EEPROM, and its feature is: the mode of erasing data and program writing data of EEPROM memory is the mode of whole page erasing and whole page writing, before erasing data, The erased page data of the EEPROM memory is also read into the page cache, page cache data, page cache data can write "0" or "1", the data to be programmed can be a whole page or a word The data to be programmed is read into the page cache, and then the data in the page cache is programmed to the corresponding page of the EEPROM memory by the whole page.

[0041] When the timing control circuit receives the write signal W, it generates a signal PE to save the page data to be erased in the page cache. That is, the page address of the page data to be erased in the EEPROM memory is decoded by the page address decoder, that is, the page address of the storage unit in the EEPROM memory is selected by the page address de...

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Abstract

The invention discloses an erasing and writing-in circuit and an erasing and writing-in method used for an EEPROM (Electrically Erasable Programmable Read-Only Memory). The erasing and writing-in circuit comprises a time sequence control module, a storage module, an input-output module, a page caching module, a page address decoder and an intra-page byte address decoder. Before the erasing and writing-in circuit and the erasing and writing-in method used for the EEPROM erase data in the EEPROM, to-be-erased page data are read in a page cache. To-be-cached page data can be written as 0 and can be also written as 1; the data needing to be programmed can be a whole page, and can be also one byte to a random number of bytes among bytes contained in one page. The erasing and writing-in circuit and the erasing and writing-in method used for the EEPROM overcome defects that the data are inflexibly written to the EEPROM, the use is unavailable on some application occasions, and a utilization rate of a storage space is low and a data writing speed is slow as the whole page is required to be written; the intra-page byte address decoder is added, the flexible input of the data into the EEPROM is realized, and the applicability is wide. A small part of the data in one page can be updated only; the utilization rate of the storage space is improved; the data writing speed is quickened.

Description

technical field [0001] The invention relates to the field of control circuits, in particular to an erasing and writing circuit for an EEPROM memory and a method thereof. Background technique [0002] Existing EEPROM erasing and writing circuits, EEPROM memory erasing data and programming and writing data modes are full-page erasing and full-page writing modes. The data to be programmed into the corresponding page of the EEPROM memory must be a whole page of data, not any byte between 1 byte and the bytes contained in a page. Generally, page cache data can only write "1" or only "0". The disadvantages of this circuit structure are: [0003] 1. Writing data to EEPROM is inflexible, and cannot be used in some applications. [0004] 2. EEPROM write data must be written in the whole page, and the utilization rate of EEPROM storage space is low. [0005] 3. For applications that only need to update a small amount of data, the speed of writing data is slow. Contents of the inv...

Claims

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Application Information

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IPC IPC(8): G11C16/10G11C16/14
CPCG11C16/10G11C16/14
Inventor 刘吉平唐伟张怀东
Owner 深圳市航顺芯片技术研发有限公司