12 results about "Byte addressing" patented technology

The invention discloses a key value storage system indexing method oriented to an NVM-NVMe SSD (Non-Volatile Memory-Non-Volatile Memory Express Solid State Disk) hybrid architecture, which comprises the following steps of: constructing a heterogeneous storage architecture taking cold and hot data perception as a core driving mechanism, coordinating and managing two types of storage media, namely a non-volatile memory NVM and a solid state disk NVMe SSD, and realizing efficient identification, layered writing and dynamic migration of cold and hot data. According to the method, the characteristics of low delay, durability and byte addressing of the NVM are utilized, the frequency and I / O overhead of Flush and Compaction operations are reduced in a data write-in path, meanwhile, the problem of mixed storage of cold and hot data is avoided, and therefore the overall performance and storage efficiency of a system are remarkably improved. In addition, by introducing an asynchronous migration module, the method can dynamically adapt to the change of data popularity along with time evolution, and effectively support high performance and high availability of the key value system in long-term operation.

The invention discloses an astronomical observation data key value storage optimization method and system based on a persistent memory. Comprising the following steps: receiving an original data stream of astronomical observation equipment, analyzing observation attribute information carried in the original data stream, generating a hierarchically coded key based on the observation attribute information, and packaging the key and a corresponding observation data value into a write-in request; accumulating the write request as batch data, distributing a continuous storage space for the batch data in a data area of a persistent memory, and writing the batch data into the distributed storage space by using a non-temporary storage instruction; updating the index structure based on the key and the storage address of the observation data value in the persistent memory; and according to the type and condition of the query request, positioning the address of the target data in the persistent memory through the index structure, and reading the data. According to the method, the nanosecond access delay and byte addressing characteristics of the persistent memory are utilized, and real-time reliable storage and rapid multi-dimensional retrieval of new-generation astronomical observation data are achieved.

The application discloses a reliable data read-write method and system based on EEPROM. A continuous N-byte address space is allocated in the EEPROM as a data storage interval for data storage. In the N-byte data storage area, (M-1) data packets are stored, wherein N is an integer multiple of 4. When reading data, adjacent storage sequence numbers in the N bytes are read in sequence according to the address sequence. If the next storage sequence number read is not continuously increased after the modulo (M+1) operation on the current storage sequence number, the current data is determined to be the latest data. The true value of the read data is determined by using a voting method among the original code, the inverse code and the exclusive or code of the stored data. The application solves the problems of low storage efficiency and poor error recovery capability in the prior art through the cyclic storage and data voting mechanism, prolongs the service life of the EEPROM and improves the reliability of data read-write.

The invention provides a storage controller, a storage system and electronic equipment, and belongs to the technical field of electronic equipment. The storage controller comprises an error positioning unit, a data processing unit and an error correction unit, the error positioning unit is connected with the processor, the storage and the data processing unit, the processor outputs a first read instruction, first data is read from the storage to perform error byte positioning, and if error bytes exist, the error correction unit performs error correction; sending the error byte address to a processor and a data processing unit; the data processing unit is connected with the processor and the error correction unit, receives a first write instruction output by the processor to the error byte address, and sends a correct byte corresponding to the error byte address included in the first write instruction and the error byte address to the error correction unit; the error correction unit is connected with the processor and the memory, performs ECC coding on correct bytes and writes correction codes into the memory; receiving a second read instruction output by the processor; and the data processing unit receives the second read instruction, obtains correct bytes and outputs the correct bytes to the processor.

The present invention relates to a memory management apparatus and a memory management method. The memory management method according to one embodiment may comprise steps in which: an I / O (input / output) classifier determines whether I / O requests are latency-sensitive; a queue management module classifies the latency-sensitive I / O requests into a fast-queue, so as to copy a memory to a host memory; the queue management module classifies, into a batch-queue, the latency-insensitive I / O requests; a queue processing module generates a scatter-gather list (SGL) for RDMA if the I / O requests classified into the batch-queue is accumulated and satisfies a predetermined flushing condition; the queue processing module transmits a request for registration to a byte-addressable storage on the basis of the generated SGL for the I / O requests; and the queue processing module generates the SGL for other I / O requests classified into the batch-queue until a response to the request for registration is received.

To provide a game machine provided with a program of a smaller size capable of initializing a main RAM respectively relating to a work area inside a use area and a work area outside the use area.SOLUTION: The initialization means of the game machine stores the value of the address of two bytes relating to one start position selected as the start position of a prescribed range in a storage determination area and determines the initialization start position of a second storage means corresponding to the value of the low-order address of the address stored in the storage determination area. Then, the first storage means is initialized from the selected initialization start position of the first storage means, and the second storage means is initialized from the determined initialization start position of the second storage means.SELECTED DRAWING: Figure 185

The present invention provides a gaming machine that can initialize the main RAM for both the working area within the used area and the working area outside the used area. [Solution] The gaming machine of the present invention has an initialization means for initializing a predetermined range of a read / write memory. The read / write memory consists of a first storage means for storing data directly related to the progress of the game and a second storage means for storing data not directly related to the progress of the game. The initialization start position of the first storage means is represented by a 2-byte address, and the final initialization position is set as a fixed address, one for each of the first and second storage means. The initialization means stores the value of the 2-byte address related to the initialization start position in a storage determination area, and can determine the address of the initialization start position of the second storage means according to the value of the lower address of the address.

A method and system including a computer-readable medium describes a byte-stream processing pipeline using the instruction set architecture of a hardware integrated circuit. The byte-stream pipeline is used to access the memory banks of a computation tile in the circuit based on instructions executed on the computation tile. Opcodes are identified within the instructions. Opcodes indicate the operation to access the memory bank of memory on the tile. From the opcodes, a byte-addressing sequence is generated to access contiguous bytes of different lengths stored in the bank. Based on the byte-addressing sequence, multiple byte-addressable memory accesses are performed in memory to retrieve multiple input vectors from the memory bank.

This application provides a method, apparatus, and device for simultaneous downloading and playback of video streaming media based on local block caching. The method obtains video playback requests and parses the media resource's Uniform Resource Locator (URL), locating it in a preset local cache space within the local file system. It then scans the various segmented cache files stored in the local cache space to construct a byte-addressable segmented cache index in memory, composed of multiple closed byte ranges. Based on the segmented request instructions parsed from the video playback request, it extracts the target byte request range and performs range matching with the byte-addressable segmented cache index. Finally, based on the matching results, it assembles and outputs the read segmented data and the acquired real-time stream data. This application, through its byte-addressable segmented cache index mechanism, solves the problem of data duplication caused by the lack of an intelligent segmented cache index mechanism in existing technologies, effectively improving cache reuse rate and playback smoothness.

The invention discloses a high-compatibility communication data processing method and system, and the method comprises the steps: unifying register addressing by taking double bytes as a unit, building a mapping relation from a register byte address to a double-byte buffer area, and calculating an index, a modulus and a shift amount based on bit operation; unified cross-boundary access operation is carried out on data possibly crossing the boundary of the buffer area. Therefore, the problems that data processing on microcontrollers (MCU) with different unit address sizes is incompatible and codes are difficult to transplant when the register length is mixed with single bytes and double bytes in a user-defined communication protocol are solved. Seamless compatibility between single-byte and double-byte MCUs is achieved, code transportability is remarkably improved, flexible access and processing of data of any initial address, length and mixed bytes are supported, and the method is suitable for scenes such as CAN communication needing high-compatibility data packaging.

Systems and methods for supporting Redundant Array of Independent Disks (RAID) are disclosed. The system may include a processor capable of issuing byte-level protocol requests including byte addresses. The system may also include a first storage device and a second storage device. The first and second storage devices may support a cache coherent interconnect protocol, which includes block-level and byte-level protocols. The first and second storage devices are included in a Redundant Array of Independent Disks (RAID). The first storage device may include a first address range, and the second storage device may include a second address range. The second storage device can provide a RAID address range associated with the first and second address ranges. A decoder associated with the second storage device may be configured to receive the request from the processor. The decoder can determine that a byte address in the RAID address range is associated with a target address range.

The invention provides a detection optimization method and system for a heterogeneous memory system. The method is applied to the detection optimization system for the heterogeneous memory system comprising a main memory and target byte addressing equipment. The detection optimization system comprises an instruction marking assembly and an instrumentation assembly which are inserted into an application program running based on the heterogeneous memory system in an instrumentation mode. The method comprises the following steps: based on an instruction marking component, detecting whether a memory address accessed based on each first instruction contained in an application program is in an address interval of target byte addressing equipment or not; if yes, recording the first instruction in a first instruction mark file; on the basis of the instrumentation component, detecting whether each second instruction contained in the application program is matched with the first instruction mark file or not; if yes, the second instruction is subjected to instrumentation based on the first detection logic, and after instrumentation is completed, the target byte addressing device is detected based on the first detection logic when it is detected that the application program accesses the target byte addressing device based on the second instruction.