Method and device for caching and transmitting of Ethernet data frames in FPGA (field programmable gate array)

Abstract

The invention discloses a method and a device for caching and transmitting of Ethernet data frames in FPGA (field programmable gate array). The method includes according to the minimum Ethernet data frame package length, deeply dividing a data frame caching and storing unit and the like into a plurality of small-particle data frame storing units; writing the Ethernet data frame into the data frame caching and storing unit, particularly storing identifiers of Ethernet data frame in a 0*0 address of an initial small-particle data frame storing unit RAM (random access memory) (n), storing sequence numbers and addresses of an initial small-particle data frame storing unit RAM (n+m) where a last byte of the Ethernet data frame existing in a 0 *1 address and a 0*2 address, and sequentially storing data frame net load byte from a 0*3 address; sequentially reading the cached data frame net load byte from the 0*3 address of the current initial small-particle data frame storing unit RAM (n) to the last byte address of the small-particle data frame storing unit RAM (n+m), and adding 1 to the sequence number n+m to read the next data frame. By the use of the method and the device, caching and transmitting of the Ethernet data frame is achieved, use ratio of RAM in the FPGA, and stability of the whole structure during the caching and transmitting is guaranteed.

Description

technical field [0001] The invention relates to buffering and forwarding of Ethernet data frames, in particular to a method and device for buffering and forwarding of Ethernet data frames in FPGA. Background technique [0002] Buffering and forwarding of Ethernet data frames is an important data exchange method between Field Programmable Gate Array (FPGA) and dedicated communication chip. According to the 802.3 protocol, a standard Ethernet data frame includes: 7-byte preamble, 1-byte frame start character, and 60-1514 bytes of payload data (including source address, destination address, length and type) ) and a 4-byte frame check sequence. [0003] When exchanging data between the FPGA and the dedicated communication chip, the FPGA will cache and forward the received Ethernet data frames. According to different considerations, there are many ways to realize the buffering and forwarding of Ethernet data frames in the FPGA. Typical methods include linked list storage method...

AI Technical Summary

Problems solved by technology

[0010] The technical problem to be solved by the present invention is the problem of low RAM utilization rate and poor stability in the FPGA during buffering and forwarding of Ethernet data frames

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