Chip packaging structure detection system
A technology of chip packaging structure and detection system, which is applied in the field of electronics, can solve problems such as insufficient testing time, material waste cost, and improvement, and achieve the effect of improving testing efficiency
Active Publication Date: 2016-11-23
SPREADTRUM COMM (SHANGHAI) CO LTD
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[0002] In the field of semiconductor technology, in order to ensure that the semiconductor devices that leave the factory meet the design requirements, the final test after chip packaging is an essential step. A series of test items are carried out according to the test requirements of semiconductor devices to ensure the functional integrity of semiconductor devices; In the post-package test of the chip, the electrostatic discharge protection test (ESD test) is an indispensable test item. Through the electrostatic discharge protection test of the chip packaging structure, the electrostatic discharge sensitivity and the electrostatic discharge withstand voltage are tested to test the chip packaging. However, in the existing technology, when the test results do not meet the characteristic parameters of the manufacturer or the user, the package is often removed and tested to find out the cause of the failure. After the test, the test is not timely enough, resulting in the waste of materials and the increase of cost
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[0036] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.
[0037] It should be noted that, in the case of no conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other.
[0038] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, but not as a limitation of the present invention.
[0039] refer to figure 1 , figure 2 , a chip package structure detection system, wherein, in forming the chip...
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The invention relates to the field of electronic technologies, in particular to a chip packaging structure detection system, which is used for implementing tests between a chip and corresponding pins during the process of lead wire bonding technology when a chip packaging structure is formed. The chip packaging structure detection system comprises a capillary provided with a metal lead wire, wherein the capillary moves along a predetermined trajectory, and is used for forming first welding points and a bank connecting the welding points on a chip as well as forming second welding points on corresponding pins; the metal lead wire is connected in a detection path; the detection path comprises a test voltage generating unit, is electrically connected with the metal lead wire, and is used for generating a test voltage of a predetermined magnitude and applying the test voltage when the first welding points or the second welding points are formed by means of the metal lead wire; and a measuring unit is connected in the detection path, and is used for acquiring detection information of the detection path. The chip packaging structure detection system applies the test voltage at the moment when the first welding points and / or the second welding points are formed, is conductive to discovering defects timely, and improves the testing efficiency.
Description
technical field [0001] The invention relates to the field of electronic technology, in particular to a chip packaging structure detection system. Background technique [0002] In the field of semiconductor technology, in order to ensure that the semiconductor devices that leave the factory meet the design requirements, the final test after chip packaging is an essential step. A series of test items are carried out according to the test requirements of semiconductor devices to ensure the functional integrity of semiconductor devices; In the post-package test of the chip, the electrostatic discharge protection test (ESD test) is an indispensable test item. Through the electrostatic discharge protection test of the chip packaging structure, the electrostatic discharge sensitivity and the electrostatic discharge withstand voltage are tested to test the chip packaging. However, in the existing technology, when the test results do not meet the characteristic parameters of the manu...
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IPC IPC(8): H01L21/66
Inventor 朱小荣
Owner SPREADTRUM COMM (SHANGHAI) CO LTD