Phase lock loop circuit and signal frequency adjusting method therefor

Abstract

Provided is a phase lock loop circuit, which comprises a phase frequency detector, a frequency control circuit, a digital control circuit and a voltage controlled oscillator. The phase frequency detector generates an error signal according to an input reference signal and a feedback signal, wherein the feedback signal is generated based on an oscillating signal. The frequency control circuit is coupled with the phase frequency detector, and receives the error signal to generate a frequency adjusting signal. The digital control circuit is coupled with the phase frequency detector, and receives the error signal to generate a digital counting signal. The voltage controlled oscillator is coupled with the frequency control circuit and the digital control circuit, and generates the oscillating signal on the basis of the frequency adjusting signal and the digital counting signal.

Description

technical field [0001] The present invention relates to a phase-locked loop circuit, and in particular to a phase-locked loop circuit and a signal frequency adjustment method thereof. Background technique [0002] In the integrated circuit design of a phase lock loop (PLL), capacitors are often the components that occupy the largest circuit area. Therefore, if the circuit area of ​​the PLL is to be reduced, it is necessary to solve the problem of capacitor space in the circuit. Generally speaking, the solution to the above problems can be to move the capacitor to the outside of the integrated circuit, and connect it to the external capacitor on the PCB board by adding an integrated circuit pin, but this method will increase the efficiency of the circuit. Design cost. Another solution is to reduce the gain (gain) of the voltage controlled oscillator (VCO) in the phase-locked loop, thereby reducing the capacitor requirement and reducing the area. [0003] However, if the VC...

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Problems solved by technology

[0003] However, when the VCO gain is greatly reduced, the tolerance of the phase-locked loop is easily deteriorated, and the phase-locked loop is easily affected by the variation of the circuit process and it is difficult to lock the frequency of the output signal.

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