Address matching circuit
An address matching and circuit technology, applied in the field of memory address detection, can solve the problems of large area, large dynamic power consumption, and many stages, and achieve the effect of small area, low power consumption, and high address matching speed
Active Publication Date: 2017-01-04
WUHAN XINXIN SEMICON MFG CO LTD
View PDF3 Cites 0 Cited by
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
like figure 1 Shown is the NOR gate structure composed of NAND gates, such as figure 2 The NOR gate structure composed of NOR gates is shown. The combined logic comparators composed of these NOR gates have disadvantages such as slow speed, many stages, large area, and large dynamic power consumption.
Method used
the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View moreImage
Smart Image Click on the blue labels to locate them in the text.
Smart ImageViewing Examples
Examples
Experimental program
Comparison scheme
Effect test
Embodiment Construction
[0037] The address matching circuit of the present invention uses a TG gate and an inverter INV to form a basic same-or / exclusive-or unit, and uses a pre-charging and parallel discharging mechanism to realize the output of a large-capacity address matching result.
[0038] Such as image 3 As shown, the address matching circuit of the present invention mainly includes a precharge circuit, several comparison circuits and several parallel discharge circuits. Wherein, the pre-charging circuit is preferably composed of a pre-charging PMOS transistor, the gate of the pre-charging PMOS transistor is connected to an enable signal EN, the source is connected to a matching signal MATCHB, and the drain and substrate are connected to the voltage VDD.
[0039] Among several comparison circuits, each comparison circuit has two input terminals (for distinguishing marks, these two input terminals are defined as the first input signal terminal and the second input signal terminal, but it shou...
the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More PUM
Login to View More Abstract
The invention relates to the field of storage address detection, in particular to an address matching circuit applied to a mass storage. The address matching circuit comprises a pre-charging circuit, a plurality of comparison circuits, and a plurality of discharging circuits which are connected in parallel, wherein an output end of the pre-charging circuit is connected to a matching signal; an output end of each comparison circuit is connected to an input end of one discharging circuit respectively; and an output end of each discharging circuit is connected in parallel to the matching signal. In the address matching circuit, a basic not exclusive or / exclusive or unit is constructed by a transmission gate and a phase inverter, so that small area, low power consumption and a high address matching speed are realized. A pre-charging mechanism and a parallel discharging mechanism are adopted, so that large-capacity address matching result output is realized.
Description
technical field [0001] The invention relates to the field of memory address detection, in particular to an address matching circuit applied to large-capacity memory. Background technique [0002] The large-capacity memory has many address bits. When it is necessary to detect a specific address of the memory, an address matching (MATCH) action is required. The high-speed characteristics of the memory require that the delay of the address MATCH action be as short as possible. [0003] Traditional address MATCH adopts NOR and XOR to form a combined logic comparator for comparison, and NOR gate and XOR gate are usually composed of a single NAND gate or NOR gate. Such as figure 1 Shown is the NOR gate structure composed of NAND gates, such as figure 2 Shown is the NOR gate structure composed of NOR gates. These combined logic comparators composed of NOR gates have disadvantages such as slow speed, many stages, large area, and large dynamic power consumption. [0004] Therefor...
Claims
the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More Application Information
Patent Timeline
Login to View More Patent Type & Authority Applications(China)
IPC IPC(8): G11C8/00
CPCG11C8/00
Inventor 王礼维
Owner WUHAN XINXIN SEMICON MFG CO LTD