Receiver for adjusting supply voltage to stabilize input overturning level

Abstract

The invention provides a receiver for adjusting a supply voltage to stabilize an input overturning level, and relates to integrated circuit technology. The receiver provided by the invention comprises an input end VIN, an output end VOUT and an inverter, as well as a slave inverter and a first operational amplifier OP1, wherein the output end of the first operational amplifier is connected with a reference point; the slave inverter is composed of a third MOS tube and a fourth MOS tube, which are serially connected between the reference point and a ground level, the third MOS tube is the same as a first MOS tube, the fourth MOS tube is the same as a second MOS tube, the substrate of the third MOS tube and the substrate of the first MOS tube are all connected to the output end of the first operational amplifier, a grid of the third MOS tube and the grid of the fourth MOS tube are all connected to a reference voltage resource, a serial connecting point of the third MOS tube and the fourth MOS tube is connected with a negative input end of the first operational amplifier OP1, and a positive input end of the first operational amplifier OP1 is connected with a second reference voltage resource with a level value of VCC / 2.

Description

technical field [0001] The present invention relates to integrated circuit technology. Background technique [0002] The receiver circuit is applied to the input terminals of various digital signals, and its flipping level is often not taken seriously in chip design, but in the application environment of long-distance signal transmission, ambient temperature change, power supply voltage change, etc., the flipping level value The stability of the circuit system has become a pivotal electrical performance, and its large drift will cause data transmission errors and even the receiver cannot work normally. [0003] Classic receiver structure: [0004] Take the TTL / CMOS signal receiver with VCC=5V as an example, since most receiving systems stipulate that the input discrimination level is: VIL (the level at which the input is determined to be low) ≤ 0.8V, VIH (the level at which the input is determined to be high) ) ≥ 2.4V, so its input flip level is usually in the range of 1.4...

AI Technical Summary

Problems solved by technology

[0008] From the aforementioned analysis of the receiver input port of the classic CMOS inverter type, it can be seen that in the application environment where the power supply voltage and temperature vary widely, the receiver input inversion level drifts greatly, and it is easy to approach VIL or VIH under certain circumstances. , so that the receiver makes an error in judging the high and low levels. On the other hand, it also greatly reduces the receiver's anti-noise ability, and data errors are prone to occur in long-distance transmission applications.

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