Lining Bias Adjustment Stabilizes Input Toggle Level Receiver

Abstract

The invention discloses a receiver for stably inputting a flip level by adjustment of a substrate bias voltage, and relates to an integrated circuit technology. The receiver comprises an input end VIN, an output end VOUT, an inverter, a subordinate inverter and a first operational amplifier, wherein the subordinate inverter consists of a third MOS transistor and a fourth MOS transistor which are connected in series between a high level VCC and a ground level, the third MOS transistor is the same as a first MOS transistor, the fourth MOS transistor is the same as a second MOS transistor, a substrate of the third MOS transistor and a substrate of the first MOS transistor are connected to an output end of the first operational amplifier OP1, a grid of the third MOS transistor and a grid of the fourth MOS transistor are connected to a reference voltage source, a series connection point between the third MOS transistor and the fourth MOS transistor is connected to a positive input end of the first operational amplifier OP1, and a negative input end of the first operational amplifier OP1 is connected with a second reference voltage source with a level value of VCC / 2. The receiver disclosed by the invention is not influenced by a supply voltage and a temperature.

Description

technical field [0001] The present invention relates to integrated circuit technology. Background technique [0002] The receiver circuit is applied to the input terminals of various digital signals, and its flipping level is often not taken seriously in chip design, but in the application environment of long-distance signal transmission, ambient temperature change, power supply voltage change, etc., the flipping level value The stability of the circuit system has become a pivotal electrical performance, and its large drift will cause data transmission errors and even the receiver cannot work normally. [0003] Classic receiver structure: [0004] Take the TTL / CMOS signal receiver with VCC=5V as an example, since most receiving systems stipulate that the input discrimination level is: VIL (the level at which the input is determined to be low) ≤ 0.8V, VIH (the level at which the input is determined to be high) ) ≥ 2.4V, so its input flip level is usually in the range of 1.4...

AI Technical Summary

Problems solved by technology

[0008] From the aforementioned analysis of the receiver input port of the classic CMOS inverter type, it can be seen that in the application environment where the power supply voltage and temperature vary widely, the receiver input inversion level drifts greatly, and it is easy to approach VIL or VIH under certain circumstances. , so that the receiver makes an error in judging the high and low levels. On the other hand, it also greatly reduces the receiver's anti-noise ability, and data errors are prone to occur in long-distance transmission applications.

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