Load current feedback stable input flip level receiver

Abstract

The invention provides a load current feedback stable input flip level receiver, and relates to the technology of integrated circuits. The load current feedback stable input flip level receiver comprises an input end VIN, an output end VOUT and a master inverter. The load current feedback stable input flip level receiver also comprises a third MOS transistor and a fourth MOS transistor which are connected in series between high level VCC and ground level, a fifth MOS transistor and a sixth MOS transistor which are connected in series between the high level VCC and the ground level, and a slave inverter which is formed by a seventh MOS transistor and an eighth MOS transistor which are connected in series between the high level VCC and the ground level, wherein the series connection point of the seventh MOS transistor and the eighth MOS transistor is connected with the positive input end of a first operational amplifier OP1, and the gate electrodes of the seventh MOS transistor and the eighth MOS transistor are connected with a reference voltage source VREF. A first MOS transistor, the third MOS transistor, the fifth MOS transistor and the seventh MOS transistor are identical in structure, and the substrates are connected with a current input end. A second MOS transistor, the fourth MOS transistor, the sixth MOS transistor and the eighth MOS transistor are identical in structure, and the substrates are connected with a current output end. The input flip level is enabled to be stable through a negative feedback control loop under the condition of increasing a small amount of chip area and power consumption without influence of power voltage or temperature.

Description

technical field [0001] The invention relates to integrated circuits, in particular to digital-analog hybrid circuits. Background technique [0002] The receiver circuit is applied to the input terminals of various digital signals, and its flipping level is often not taken seriously in chip design, but in the application environment of long-distance signal transmission, ambient temperature change, power supply voltage change, etc., the flipping level value The stability of the circuit system has become a pivotal electrical performance, and its large drift will cause data transmission errors and even the receiver cannot work normally. [0003] Classic receiver structure: [0004] Take the TTL / CMOS signal receiver with VCC=5V as an example, since most receiving systems stipulate that the input discrimination level is: VIL (the level at which the input is determined to be low) ≤ 0.8V, VIH (the level at which the input is determined to be high) ) ≥ 2.4V, so its input flip level...

AI Technical Summary

Problems solved by technology

[0008] From the aforementioned analysis of the receiver input port of the classic CMOS inverter type, it can be seen that in the application environment where the power supply voltage and temperature vary widely, the receiver input inversion level drifts greatly, and it is easy to approach VIL or VIH under certain circumstances. , so that the receiver makes an error in judging the high and low levels. On the other hand, it also greatly reduces the receiver's anti-noise ability, and data errors are prone to occur in long-distance transmission applications.

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