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Receiver control method having stable input flip level

A technology of inversion level and control method, which is applied in the direction of logic circuit connection/interface layout, logic circuit coupling/interface using field effect transistors, electrical components, etc., which can solve the problems of reducing receiver noise resistance, data error, receiving In order to achieve the effect of stable input flipping level and other problems

Active Publication Date: 2017-01-04
CHENGDU SINO MICROELECTRONICS TECH CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] From the aforementioned analysis of the receiver input port of the prior art CMOS inverter type, it can be seen that in an application environment where the power supply voltage and temperature vary widely, the receiver input inversion level drifts greatly, and it is easy to approach VIL under certain circumstances. Or VIH, which makes the receiver's judgment of high and low levels wrong. On the other hand, it also greatly reduces the receiver's anti-noise ability, and data errors are prone to occur in long-distance transmission applications.

Method used

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  • Receiver control method having stable input flip level
  • Receiver control method having stable input flip level
  • Receiver control method having stable input flip level

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Experimental program
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Embodiment 1

[0028] see Figure 4 . This embodiment utilizes the effect of the MOS tube source-liner reverse bias voltage value affecting the MOS turn-on threshold, and cooperates with the operational amplifier OP1 to Figure 4 The threshold voltage of the MP2 tube in the circuit is adjusted, and then the drift of the receiver input flipping level is compensated, so that the flipping level remains constant under different source voltages and temperature conditions.

[0029] In this embodiment, the substrate of the MOS transistor MP2 connected to the high level in the master inverter and the substrate of the MOS transistor MP1 connected to the high level in the slave inverter are connected as the common reference point of the master-slave inverter to The output of the op amp is connected to the positive input of the op amp from the output nodes of the inverter, that is, the drains of MP1 and MN1, the reference voltage VCC / 2 is connected to the negative input of the op amp, and the VREF ref...

Embodiment 2

[0034] see Figure 9 . In this embodiment, the closed-loop control of the load current of the receiver is used to make the input inversion level of the receiver equal to the set value. The input inversion level of this structure is similar to that described in structure A, and has higher temperature and source voltage suppression capabilities.

[0035] The specific working principle is to use the controllable current sources MP3 and MN3 to replace the line bias control in Embodiment 1, so as to use the current load to compensate the drift of the input inversion level under different temperatures and source voltages.

[0036] OP1 forms a closed-loop control with MP3 and MN3, so that the current load of the slave inverter composed of MP1 and MN1 is adjusted according to the change of power supply voltage and temperature, so the output voltage of the slave inverter is always VCC / 2 under the input VREF voltage , and set the size of MN4 and MP4 to be the same as MN3 and MP3, so th...

Embodiment 3

[0040] see Figure 10 . The receiver of this embodiment utilizes closed-loop control of the power supply voltage of the receiver to make the receiver input inversion level equal to the set value. The temperature coefficient of the input inversion level and the power supply suppression capability of this structure are still determined by VREF itself.

[0041] The specific working principle is to use the operational amplifier OP1 and the slave inverter itself to form a closed-loop control, and adjust the source voltage of the inverter so that the output of the slave inverter is equal to VCC / 2 under the input of VREF. Since the sizes and source voltages of the master and slave inverters are equal, and there is no influence of lining bias and DC current load, the input reversal level of the master inverter is equal to VREF.

[0042] On the one hand, this embodiment does not need to introduce an additional power supply, and at the same time has a strong adjustment capability; on t...

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Abstract

The invention relates to a receiver control method having a stable input flip level and belongs to the technical field of an integrated circuit. The receiver control method comprises steps that a correction level signal is applied to a flip level control point of a main inverter of a receiver, the correction level signal is an output signal of a closed loop control circuit formed by an operation amplifier and a secondary inverter which is identical to the main inverter in structure and parameters, and the output signal is an output signal of the operation amplifier; for the closed loop control circuit, the position of a flip level control point in the secondary inverter is correspondingly identical to the position of the flip level control point in the main inverter, the secondary inverter is connected with an output end of the operation amplifier through the flip level control point, an output end of the secondary inverter is connected with a positive input end of the operation amplifier, an input end of the secondary inverter is connected with one reference voltage VREF, and a negative input end of the operation amplifier is connected with a second reference level. According to the receiver control method, the input flip level is made to be stable through a negative feedback control loop, and influence of a power source voltage and temperature can be avoided.

Description

technical field [0001] The present invention relates to integrated circuit technology. Background technique [0002] The flipping level of the input port of a digital circuit is often not taken seriously in chip design, but in the application environment such as long-distance signal transmission, ambient temperature change, power supply voltage change, wide voltage range receiver, etc., the stability of the flipping level value It has become an important electrical performance in the circuit system, and its large drift will cause data transmission errors and even the receiver cannot work normally. Therefore, it is necessary to carry out a specific optimized design for the input port to improve the receiver's ambient temperature, power supply voltage suppression capability and work stability, so that the receiver can work normally in various application environments. [0003] Take the TTL / CMOS signal receiver with VCC=5V as an example, since most receiving systems stipulate ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K19/0185H03K19/003
CPCH03K19/00384H03K19/018507
Inventor 李大刚刁小芃张克林林立爽黄俊杰刘范宏
Owner CHENGDU SINO MICROELECTRONICS TECH CO LTD