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Receiver with Stable Input Toggle Level

A technology of inverting level and receiver, applied in the direction of logic circuit connection/interface arrangement, logic circuit coupling/interface using field effect transistor, logic circuit, etc. Data errors, etc., to achieve the effect of stable input inversion level

Active Publication Date: 2019-07-05
CHENGDU SINO MICROELECTRONICS TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] From the aforementioned analysis of the receiver input port of the prior art CMOS inverter type, it can be seen that in an application environment where the power supply voltage and temperature vary widely, the receiver input inversion level drifts greatly, and it is easy to approach VIL under certain circumstances. Or VIH, which makes the receiver's judgment of high and low levels wrong. On the other hand, it also greatly reduces the receiver's anti-noise ability, and data errors are prone to occur in long-distance transmission applications.

Method used

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  • Receiver with Stable Input Toggle Level
  • Receiver with Stable Input Toggle Level
  • Receiver with Stable Input Toggle Level

Examples

Experimental program
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Effect test

Embodiment 1

[0028] see Figure 4 . In this embodiment, the effect of the MOS tube source-liner reverse bias voltage value affecting the MOS turn-on threshold is used, and the operational amplifier OP1 is used to Figure 4 The threshold voltage of the MP2 tube in the circuit is adjusted, and then the drift of the receiver input flipping level is compensated, so that the flipping level remains constant under different source voltages and temperature conditions.

[0029] In this embodiment, the substrate of the MOS transistor MP2 connected to the high level in the master inverter and the substrate of the MOS transistor MP1 connected to the high level in the slave inverter are connected as the common reference point of the master-slave inverter to The output of the op amp is connected to the positive input of the op amp from the output nodes of the inverter, that is, the drains of MP1 and MN1, the reference voltage VCC / 2 is connected to the negative input of the op amp, and the VREF referenc...

Embodiment 2

[0034] see Figure 9 .

[0035] A receiver with a stable input toggle level, consisting of the following:

[0036] The main inverter includes a second PMOS transistor MP2 and a second NMOS transistor MN2 connected in series between the high-level input terminal VCC (the voltage value is VCC) and the ground level, and the drain connection point of the two is connected to the second operation Put the positive input terminal of OP_ASS, the gates of the two are connected to the receiver input terminal VIN and connected to the output terminal of the second op amp OP_ASS; the main inverter also includes a high-level input terminal VCC and ground level in series Between the fourth PMOS transistor MP4 and the fourth NMOS transistor MN4, the drain connection points of the two are connected to the positive input terminal of the second operational amplifier OP_ASS, and the gates of the two are connected to the output terminal of the first operational amplifier OP1; The voltage value of...

Embodiment 3

[0045] see Figure 10 . The receiver of this embodiment utilizes closed-loop control of the power supply voltage of the receiver to make the receiver input inversion level equal to the set value. The temperature coefficient of the input inversion level and the power supply suppression capability of this structure are still determined by VREF itself.

[0046] The specific working principle is to use the operational amplifier OP1 and the slave inverter itself to form a closed-loop control, and adjust the source voltage of the inverter so that the output of the slave inverter is equal to VCC / 2 under the input of VREF. Since the sizes and source voltages of the master and slave inverters are equal, and there is no influence of lining bias and DC current load, the input reversal level of the master inverter is equal to VREF.

[0047] On the one hand, this embodiment does not need to introduce an additional power supply, and at the same time has a strong adjustment capability; on t...

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Abstract

The invention relates to a receiver control method having a stable input flip level and belongs to the technical field of an integrated circuit. The receiver control method comprises steps that a correction level signal is applied to a flip level control point of a main inverter of a receiver, the correction level signal is an output signal of a closed loop control circuit formed by an operation amplifier and a secondary inverter which is identical to the main inverter in structure and parameters, and the output signal is an output signal of the operation amplifier; for the closed loop control circuit, the position of a flip level control point in the secondary inverter is correspondingly identical to the position of the flip level control point in the main inverter, the secondary inverter is connected with an output end of the operation amplifier through the flip level control point, an output end of the secondary inverter is connected with a positive input end of the operation amplifier, an input end of the secondary inverter is connected with one reference voltage VREF, and a negative input end of the operation amplifier is connected with a second reference level. According to the receiver control method, the input flip level is made to be stable through a negative feedback control loop, and influence of a power source voltage and temperature can be avoided.

Description

technical field [0001] The present invention relates to integrated circuit technology. Background technique [0002] The flipping level of the input port of a digital circuit is often not taken seriously in chip design, but in the application environment such as long-distance signal transmission, ambient temperature change, power supply voltage change, wide voltage range receiver, etc., the stability of the flipping level value It has become an important electrical performance in the circuit system, and its large drift will cause data transmission errors and even the receiver cannot work normally. Therefore, it is necessary to carry out a specific optimized design for the input port to improve the receiver's ambient temperature, power supply voltage suppression capability and work stability, so that the receiver can work normally in various application environments. [0003] Take the TTL / CMOS signal receiver with VCC=5V as an example, since most receiving systems stipulate ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03K19/0185H03K19/003
CPCH03K19/00384H03K19/018507
Inventor 李大刚刁小芃张克林林立爽黄俊杰刘范宏
Owner CHENGDU SINO MICROELECTRONICS TECH CO LTD