A cache allocation, data access, data transmission method, processor and system

Abstract

Disclosed are cache distribution, data access and data sending methods, processors, and a system. The cache distribution method comprises: a second processor receives an access request, sent by a first processor, for acquiring first data, wherein the first data is not stored in a cache of the first processor and is stored in a cache of the second processor, and the access request comprises a cache utilization rate of each processor on a path between the first processor and the second processor; the second processor determines a processor, having the cache utilization rate lower than the cache utilization rate of the second processor, among all the processors as a borrowed processor; and the second processor sends the first data to a cache of the borrowed processor, and instructs the borrowed processor to send the first data to the first processor, wherein the first processor, the second processor, and the borrowed processor pertain to the same multi-processor system.

Description

technical field [0001] The present invention relates to the field of computer technology, in particular to a buffer allocation, data access, data sending method, processor and system. Background technique [0002] Today's computer systems are usually multi-processor systems, that is, they are composed of multiple processors, and there are multiple processor cores in one processor. Each processor has its own cache, where data is stored for the processor to access. How to provide data for multiple processors in a timely and effective manner has become a key issue in the design of cache structures for multiprocessor systems. [0003] The cache structure of the existing multiprocessor system is designed as a cooperative cache. For each processor, in addition to the first-level private cache, the second-level cache of each processor is divided into two parts, one part is used for local private use, and the other part is used for global sharing. The size of the private part and...

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Problems solved by technology

[0004] Therefore, the deficiencies in the design of the cache structure of the cooperative cache are: the cache capacity of the processor is limited, and it cannot cope with the situation that the processor's local private cache capacity is greater than the secondary cache capacity, or the processor's The case where the global shared cache capacity requirement is greater than the secondary cache capacity

[0005] Therefore, the cache structure design of the existing multiprocessor system is unreasonable, and the cache capacity of the processor is limited.

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