Microprocessor and method of performing fused compound arithmetic operations within a microprocessor
An arithmetic operation, microprocessor technology, applied in machine execution devices, concurrent instruction execution, electrical digital data processing, etc., can solve problems such as performance disadvantages
Active Publication Date: 2021-01-22
VIA ALLIANCE SEMICON CO LTD
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[0010] However, in cases where adders and multipliers of multiple split FMA functions share the same dispatch port, the above configuration suffers a performance disadvantage when FMA instructions saturate the pipeline
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[0038] The following description is presented to enable one of ordinary skill in the art to make and use the invention as presented within the context of the particular application and its requirements. However, various modifications to the preferred embodiment will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments as well. Thus, the present invention is not intended to be limited to the particular embodiments shown and described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
[0039] Figure 1-8 Various aspects of various embodiments of the invention are illustrated. figure 1 was applied from '817 figure 1 modified, and use consistent reference numerals. Since the '817 application uses reference numerals up to 500, the present application Figure 2-8 Reference numbers starting with the 600 range are used from the end of the '817 a...
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The present invention relates to a microprocessor and a method of performing fused compound arithmetic operations within the microprocessor. The microprocessor is configured for unchained and chained modes that incorporate split execution of compound arithmetic operations. In these two modes of split execution, the first instruction execution unit executes only the first part of the fused compound arithmetic operation and produces its intermediate result, and the second instruction execution unit receives the intermediate result and executes the second part of the fused compound arithmetic operation. section to produce the final result. In the unchained mode, execution is achieved by dispatching individual split-execution microinstructions to the first instruction execution unit and the second instruction execution unit. In chained mode, a single split-execution microinstruction is dispatched to a first instruction execution unit and a chained control signal or signal group is sent to a second instruction execution unit so that the second instruction execution unit operates without an instruction Perform the second part of the fused compound arithmetic operation to implement the execution.
Description
[0001] Cross References to Related Applications [0002] This application claims priority to US Provisional Patent Application 62 / 236,529, filed October 2, 2015, which is hereby incorporated by reference. [0003] This application is related to U.S. Patent Application 14 / 748,817, entitled "Non-atomic Split-Path FusedMultiply-Accumulate," filed June 24, 2015 (the "'817 application"), which claims the July 2, 2014 U.S. Provisional Patent Application 62 / 020,246, filed on June 10, 2015, entitled "Non-Atomic Split-Path Fused Multiply-Accumulate with Rounding cache" and entitled "Non-Atomic Temporally-Split Fused Multiply-Accumulate with Rounding cache" and Operation Using a Calculation Control Indicator Cache and Providing a Split-Path Heuristic for Performing a Fused FMA Operation and Generating a StandardFormat Intermediate Result", which are hereby incorporated by reference in their entirety. [0004] This application is also related to and incorporates by reference the following...
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IPC IPC(8): G06F7/544G06F7/575G06F9/22G06F9/28G06F9/302G06F9/38
CPCG06F7/5443G06F7/575G06F9/223G06F9/28G06F9/3001G06F9/3867G06F9/3887G06F9/3893G06F9/30014G06F9/3836
Inventor 汤玛士·艾欧玛尼基尔·A·帕蒂尔
Owner VIA ALLIANCE SEMICON CO LTD