Multi-core system-based hardware watchdog control method and system

Abstract

The invention discloses a multi-core system-based hardware watchdog control method and system. The method comprises the steps that a master core processor starts a multi-task mode and sends a master core processor heartbeat message to a slave core processor every a first predetermined time; the slave core processor receives the master core processor heartbeat message sent by the master core processor and sends slave core processor heartbeat information to the master core processor after receiving the master core processor heartbeat message; and when it is detected that the master core processor receives the slave core processor heartbeat information sent by the slave core processor and the master core processor performs task switching, a watchdog is cleared. According to the method and the system, the master core processor is in charge of clearing the watchdog; a heartbeat mechanism is established between the master core processor and the slave core processor; the master core processor performs watchdog clearing operation only when the heartbeat of the slave core processor is detected and the master core processor performs task switching, so that multiple cores are not reset by the watchdog during normal running; and the whole system can be reset once inter-core communication is interrupted, one or more cores are abnormal due to crash or the like.

Description

technical field [0001] The invention relates to the technical field of embedded systems, in particular to a hardware watchdog control method and system based on a multi-core system. Background technique [0002] In the embedded application field, in order to prevent the system from crashing, or to ensure the real-time performance of the system and prevent a certain task from running for a long time, it is very common to use a hardware watchdog mechanism. The hardware watchdog is implemented by hardware circuits or related chips. If it is not reset within a certain period of time (usually 1.6 seconds), the watchdog will automatically pull down the #RESET signal of the CPU to hard reset the CPU. From this point of view, it is necessary for the watchdog to play a role, and it cannot be allowed to reset the system by mistake. The general method is to clear the dog regularly by the application program. The methods include: interrupt the clearing dog at tick, clear the dog in the...

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Problems solved by technology

[0005] In view of the deficiencies in the prior art, the purpose of the present invention is to provide a hardware watchdog control method and system based on a multi-core system, aiming to solve the problem of using the WATCHDOG_TIMER provided by the hardware core in the prior art, which can only reset the core where it is located, Cannot reset all the cores in the CPU chip

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