A dual-port memory word line control circuit

Abstract

The invention provides a dual-port memory word line control circuit. The dual-port memory word line control circuit includes: a control module which is used for generating two control signals according to a read-write enable signal, an EDAC open enable signal, and a dual-port address comparison signal of a memory port; a clock delay module which is used for generating four delay signals according to a clock signal and two delay control signals; and a word line control signal generation module which is electrically connected to the control module and the clock delay module and is used for generating a word line control signal according the two control signals and the four delay signals. The dual-port memory word line control circuit can generate the word line control signal having an error correction function, can complete data read-out and write-back during a clock period, and can store corrected data without redundant memory units, thereby decreasing the chip area; and the dual-port memory word line control circuit is compatible with a dual-port memory word line control circuit without an EDAC function.

Description

technical field [0001] The invention relates to the technical field of memory, in particular to a dual-port memory word line control circuit. Background technique [0002] Memory is one of the commonly used devices in digital systems. With the increase of the memory chip capacity, the yield of the device decreases exponentially. On the other hand, under different application environments, the storage unit (bit-cell) of the static random access memory (SRAM) may be flipped, resulting in the loss of stored data. mistake. Therefore, when designing a memory circuit, it is necessary to use an error detection and correction (EDAC for short) circuit to perform data error correction and write back to improve the reliability of the memory. [0003] Generally, the EDAC circuit can correct errors of one or more storage units according to different error correction codes and data bit widths, and then output correct data. However, if the error data of the storage unit is not corrected...

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Problems solved by technology

At the same time, the above method needs to introduce a new control trigger signal to judge when to write redundant data back to the memory, which increases the generation circuit of the signal and makes the hardware design more complicated

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