Memory cell device and manufacturing method thereof

Abstract

The invention discloses a memory cell device, comprising: a gate ONO layer, a gate electrode material layer and side walls, a source region and a drain region are self-aligned with corresponding side walls respectively, a gate electrode material layer and source and drain on both sides The region does not overlap at all; the channel region includes the gate-controlled channel region covered by the gate electrode material layer and the conduction channel region on both sides of the gate-control channel region; the conduction channel region and the corresponding source or drain region It overlaps and is used to realize the connection between the channel of the gate-controlled channel region and the source-drain region; by adjusting the distance between the source region and the drain region and the ratio of the width of the gate electrode material layer and the conductance of the conduction channel region The on-resistance is used to increase the anti-drain disturbance capability of the memory cell device. The invention also discloses a manufacturing method of the memory unit device. The invention can greatly improve the drain interference, and can ensure that the characteristics of the programming, erasing and reading operations of the storage device are basically unchanged, and the area of ​​the unit device can not be changed.

Description

technical field [0001] The invention relates to the field of manufacturing semiconductor integrated circuits, in particular to a memory unit device; the invention also relates to a method for manufacturing the memory unit device. Background technique [0002] Memory (Memory) includes an array structure composed of multiple unit (Cell) devices. The unit devices of non-volatile memory generally use SONOS devices. In SONOS devices, ONO represents the bottom oxide layer, the middle nitride layer and the top oxide layer. The bottom of the gate ONO layer is a semiconductor substrate such as a silicon substrate, and the semiconductor substrate is represented by S; the top of the gate ONO layer is a gate electrode material layer, and the gate electrode material layer is generally polysilicon gate, so it is also represented by S; English letters together represent SONOS devices. Among them, the bottom oxide layer is a tunneling oxide layer, which is used to realize the tunneling pro...

AI Technical Summary

Problems solved by technology

As shown in Table 1, when the Target is programmed, the V of the unit device corresponding to B WLS i.e. gate voltage V G -4.5V~-2.0V, and V BL That is, the drain voltage V D is 0.6V~2.1V, which will make the V of the unit device corresponding to B D and V G The voltage difference is large, which is prone to drain interference, that is, if the B memory cell is under this bias for a long time, the charge stored in the B cell will be lost due to the tunneling effect of the charge, which will cause errors in the stored data.

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