Memory unit device and manufacture method thereof

Abstract

The present invention discloses a memory unit device. The memory unit device comprises a gate ONO layer, a gate electrode material layer and side walls. A source region and a drain region respectively align with corresponding side walls. The gate electrode material layer is not overlaid with the source region and the drain region at two sides completely. A channel region comprises a gate control channel region covered by the gate electrode material layer and conductive channel regions at two sides of the gate control channel region. The conductive channel region and the corresponding source region or drain region are overlaid and are used for connection between the channel of the gate control channel region and the source and drain regions. An anti-drain disturb capacity of the memory unit device is improved by adjusting a ratio of a distance between the source region and the drain region to a width of the gate electrode material layer, and a conductive resistance of the conductive channel region. The present invention further discloses a manufacture method of the memory unit device. The anti-drain disturb capacity is improved, characteristics of operations like programming, erasing, and reading of the memory device are generally maintained, and the area of the unit device is not changed.

Description

technical field [0001] The invention relates to the field of manufacturing semiconductor integrated circuits, in particular to a memory unit device; the invention also relates to a method for manufacturing the memory unit device. Background technique [0002] Memory (Memory) includes an array structure composed of multiple unit (Cell) devices. The unit devices of non-volatile memory generally use SONOS devices. In SONOS devices, ONO represents the bottom oxide layer, the middle nitride layer and the top oxide layer. The bottom of the gate ONO layer is a semiconductor substrate such as a silicon substrate, and the semiconductor substrate is represented by S; the top of the gate ONO layer is a gate electrode material layer, and the gate electrode material layer is generally polysilicon gate, so it is also represented by S; English letters together represent SONOS devices. Among them, the bottom oxide layer is a tunneling oxide layer, which is used to realize the tunneling pro...

AI Technical Summary

Problems solved by technology

As shown in Table 1, when the Target is programmed, the V of the unit device corresponding to B WLS i.e. gate voltage V G -4.5V~-2.0V, and V BL That is, the drain voltage V D is 0.6V~2.1V, which will make the V of the unit device corresponding to B D and V G The voltage difference is large, which is prone to drain interference, that is, if the B memory cell is under this bias for a long time, the charge stored in the B cell will be lost due to the tunneling effect of the charge, which will cause errors in the stored data.

Images