Forward and reverse scanning gate drive circuit
A gate drive circuit, forward and reverse scanning technology, applied in the direction of static indicators, instruments, etc., can solve the problems of pre-filling module M1 asymmetry, the circuit cannot operate normally, etc., and achieve a good maintenance effect
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Embodiment 1
[0035] Such as figure 2 As shown, a forward and reverse scanning gate drive circuit includes a forward pre-charge module (01), a reverse pre-charge module (02), a pull-up module (03), a gate scan signal maintenance module (04), Forward maintenance module (05), reverse maintenance module (06), auxiliary maintenance module (07), empty reset module (08) and bootstrap capacitor (C1); among them, the forward precharge module (01), reverse The connection points of pre-charge module (02), pull-up module (03), forward sustain module (05), reverse sustain module (06), auxiliary sustain module (07) and bootstrap capacitor (C1) are pull-up control Node (netAn); the connection point of the pull-up module (03), the gate scanning signal maintenance module (04), and the bootstrap capacitor (C1) is the gate scanning signal (Gn); the gate scanning signal maintenance module (04) , the forward sustaining module (05), the reverse sustaining module (06), and the auxiliary sustaining module (07) ...
Embodiment 2
[0050] The difference between this embodiment and Embodiment 1 lies in that the specific circuits of the forward sustaining module (05) and the reverse sustaining module (06) are different. Such as Figure 5 As shown, in this embodiment, the forward sustaining module (05) includes a forward sustaining first TFT (M5), a forward sustaining second TFT (M6), a forward sustaining third TFT (M6A), and a forward sustaining TFT (M6A). Maintaining the fourth thin film transistor (M8) and sustaining the discharge thin film transistor (M7) in the forward direction; wherein the source of the first thin film transistor (M5) in the forward direction is connected to the forward scanning control signal (U2D), and the gate is connected to the mth- 1 clock signal (CKm-1), the drain and the source of the second TFT (M6), the source of the third TFT (M6A), and the fourth TFT (M8) The gate of the gate is connected to the source of the forward maintaining discharge thin film transistor (M7), and the...
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