Anti-single-event upset D trigger

An anti-single event and trigger technology, applied in the direction of pulse technology, pulse generation, electrical components, etc., can solve the problem of low anti-single event flipping ability, and achieve the effect of improving the anti-single event flipping ability

Active Publication Date: 2017-03-15
SHENZHEN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] An embodiment of the present invention provides a D flip-flop that is resistant to single-event upsets, aiming to solve the problem that the anti-single-event upset capability of the D flip-flop is not high in the prior art

Method used

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  • Anti-single-event upset D trigger

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Embodiment Construction

[0021] In order to make the purpose, features, and advantages of the embodiments of the present invention more obvious and understandable, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, The described embodiments are only some, but not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative efforts belong to the protection scope of the present invention.

[0022] see figure 1 , figure 1 It is a schematic diagram of the circuit structure of the C unit circuit based on the DICE structure, and the C unit circuit based on the DICE structure includes:

[0023] A first signal input terminal IN1, a second signal input terminal IN2, a signal output terminal OUT, a P-channel MOS transistor MP1, a P-...

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Abstract

The present invention is applied to the D trigger technology field, and provides an anti-single-event upset D trigger. The D trigger comprises a clock signal input circuit, a main latch buffer circuit, a slave latch buffer circuit, a main latch and a slave latch. The main latch and the slave latch are both dual-mode redundant reinforcing latches. Compared to the prior art, buffer circuits are added at the fronts of the main latch and the slave latch to improve the anti-single-event upset capacity of the D trigger, the main latch and the slave latch are subjected to dual-mode redundant reinforcing to separate into pull-up PMOS tubes and pull-down NMOS tubes, which are mutually redundant, in C2MOS circuits so as to avoid the feedback loop caused by the single-particle transient pulse in the slave latch, the C2MOS circuits in the main latch and the slave latch circuits are improved, and the control of the circuits through clock signals is realized through the CMOS transmission gate so as to further improve the anti-single-event upset capacity of the D trigger.

Description

technical field [0001] The invention belongs to the technical field of D flip-flops, in particular to a D flip-flop resistant to single-event reversal. Background technique [0002] There are a large number of high-energy particles (protons, electrons, heavy ions, etc.) in the universe. After the sequential circuit in the integrated circuit is bombarded by these high-energy particles, the state it maintains may be reversed. This effect is called the single event reversal effect. The higher the LET (Linear Energy Transfer) value of the bombardment IC, the easier it is to produce single event upset effects. After the combined circuit in the integrated circuit is bombarded by these high-energy particles, it is possible to generate a transient electric pulse. This effect is called the single event transient effect. The higher the LET value of the single particle bombarding the integrated circuit, the longer the duration of the generated transient electric pulse , the electrical...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K3/3562
Inventor 贺威贺凌翔张准骆盛吴庆阳
Owner SHENZHEN UNIV
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