Method and apparatus for detecting hang of FPGA chip

A chip and switching chip technology, applied in the field of network communication, can solve problems such as poor real-time performance

Active Publication Date: 2017-03-15
HANGZHOU DPTECH TECH
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[0004] In view of this, the present application provides a method and device for detecting FPGA ch

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  • Method and apparatus for detecting hang of FPGA chip
  • Method and apparatus for detecting hang of FPGA chip
  • Method and apparatus for detecting hang of FPGA chip

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[0017] Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numerals in different drawings refer to the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with aspects of the present application as recited in the appended claims.

[0018] The terminology used in this application is for the purpose of describing particular embodiments only, and is not intended to limit the application. As used in this application and the appended claims, the singular forms "a", "the", and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should also be understood that the term...

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Abstract

The application provides a method and apparatus for detecting the hang of an FPGA chip, the method comprising: obtaining, within a preset time period, a packet receiving statistical value and a packet transmitting statistical value for each port on a switch chip and a packet loss statistical value of a port on the FPGA chip connected to the port, and determining whether the packet transmitting statistical value is not zero and the sum of the packet receiving statistical value and the packet loss statistical value is less than a first predetermined value, and if so, adding 1 to an error number; determining whether the error number is higher than a second preset value; if so, determining the hang of the FPGA chip. The method and apparatus determine whether the port is faulted according to the packet receiving statistical value, packet transmitting statistical value and the packet loss statistical value, and can determine whether the FPGA chip is subjected to hang according to the number of error ports, prevents manual detection, improves real-timeness of the detection.

Description

technical field [0001] The present application relates to the technical field of network communication, and in particular to a method and device for detecting hangup of an FPGA chip. Background technique [0002] Currently, FPGA (Field-Programmable Gate Array, Field Programmable Gate Array) chips are used in network devices to process packets, so as to share the CPU's workload on packet processing and analysis, and improve packet forwarding performance. Using the FPGA chip for message business processing, on the one hand, frees the CPU from fatigue in dealing with high-speed data traffic processing, speeds up message classification and processing speed, and on the other hand, makes message forwarding more stable. Therefore, in network communication, the FPGA chip is in a crucial position. If the FPGA chip hangs up, it will cause business interruption. [0003] In the related technology, through the monitoring system of the management equipment, the management personnel obse...

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Application Information

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IPC IPC(8): H04L12/26
CPCH04L43/08H04L43/0829H04L43/16
Inventor 王亚亮刘小兵
Owner HANGZHOU DPTECH TECH
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