Output port circuit

Abstract

The invention provides an output port circuit. The output port circuit comprises a signal generating module, which is used to receive an input signal, an enabling signal, and an enabling inverted signal respectively, and is used to generate a first signal and a second signal according to the enabling signal and the enabling inverted signal. The rising edge of the first signal is ended before the ending of the rising edge of the second signal, and the falling edge of the second signal is ended before the ending of the falling edge of the first signal. A first output module is respectively connected with the first output end of the signal generating module and an output port, and the first output module is used to receive the first signal, and when the first signal is in a low level, the input signal is output to the output port. A second output module is respectively connected with the second output end of the signal generating module and the output port, and the second output module is used to receive the second signal, and when the second signal is in a high level, the input signal is output to the output port. By adopting the output port circuit, the simultaneous conduction of the first output module and the second output module is prevented, and transient peak current and circuit power consumption are effectively reduced.

Description

technical field [0001] The invention relates to the technical field of circuits, in particular to an output port circuit. Background technique [0002] The structure of the traditional output port circuit is as figure 1 As shown, the input signal (DATA') is connected to one input terminal of the NAND gate (V') and the NOR gate (U'), and the other input terminal of the NAND gate (V') is connected to the enable signal (EN' ), the other input terminal of the NOR gate (U') is connected to the enable negative signal (ENB'), the output terminal of the NAND gate (V') is A', and the output terminal of the NOR gate (U') is B ', the gate terminal of the P-type field effect transistor P1' is connected to A', and the gate terminal of the N-type field effect transistor N1' is connected to B'. The drain terminals of the P-type field effect transistor P1' and the N-type field effect transistor N1' are connected to the output port (PAD'), the source terminal of the P-type field effect tra...

AI Technical Summary

Problems solved by technology

[0004] In view of the above problems, the purpose of the embodiments of the present invention is to provide an output port circuit to solve the problem of large power consumption of the entire circuit when the P-type field effect transistor P1' and the N-type field effect transistor N1' are turned on at the same time

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