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3D semiconductor device

A semiconductor, three-dimensional technology, applied in the field of three-dimensional semiconductor devices, can solve problems such as limitations

Active Publication Date: 2021-12-28
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, since extremely expensive equipment is required to form fine patterns, the integration density of two-dimensional (2D) semiconductor devices continues to increase, but it is still limited

Method used

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Embodiment Construction

[0029] Exemplary embodiments of aspects of the inventive concepts shown and explained herein include their complementary counterparts. Throughout the specification, the same reference numerals or the same reference numerals denote the same elements.

[0030] figure 1 is a schematic block diagram illustrating a three-dimensional (3D) semiconductor device according to some embodiments of the inventive concept.

[0031] refer to figure 1 , the 3D semiconductor device may include a memory cell array 1, a row decoder 2, a page buffer 3, a column decoder 4 and a control circuit 5. The 3D semiconductor device may be a 3D semiconductor memory device.

[0032] The memory cell array 1 may include a plurality of memory blocks BLK0 to BLKn. Each of the memory blocks BLK0 to BLKn may include a plurality of memory cells, a plurality of word lines, and a plurality of bit lines. Word lines and bit lines can be electrically connected to the memory cells.

[0033] The row decoder 2 may dec...

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PUM

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Abstract

Disclosed is a three-dimensional (3D) semiconductor device comprising: a stack structure including electrodes vertically stacked on a substrate; a channel structure coupled to the electrodes to constitute a plurality of memory cells three-dimensionally arranged on the substrate, the channel structure including a first vertical channel and a second vertical channel passing through the stack structure and a first horizontal channel disposed below the stack structure so as to laterally connect the first vertical channel and the second vertical channel to each other; The second horizontal channel has the first conductivity type and is connected to the sidewall of the first horizontal channel of the channel structure; the conductive plug has the second conductivity type and is disposed on the top end of the second vertical channel.

Description

[0001] This application claims priority from Korean Patent Application No. 10-2015-0132515 filed with the Korean Intellectual Property Office on September 18, 2015, the disclosure of which is hereby incorporated by reference in its entirety. technical field [0002] The inventive concepts relate to three-dimensional (3D) semiconductor devices, and more particularly, to 3D semiconductor devices capable of improving reliability and integration density. Background technique [0003] Semiconductor devices have been highly integrated to provide high performance and low cost. The integration density of semiconductor devices affects the cost of semiconductor devices, thus creating a demand for highly integrated semiconductor devices. The integration density of conventional two-dimensional (2D) or planar semiconductor devices may be mainly determined by the area occupied by a unit memory cell. Therefore, the integration density of conventional two-dimensional (2D) semiconductor dev...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/11597H01L27/11551
CPCH10B41/20H10B51/20H10B43/10H10B43/40H10B43/27H10B41/35H10B43/30H10B43/35H01L23/535H01L23/5283
Inventor 李昌炫李宪奎姜信焕朴泳雨
Owner SAMSUNG ELECTRONICS CO LTD