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Method of forming semiconductor device including conductive contacts on source/drain

A conductive contact and semiconductor technology, applied in the electronic field, can solve problems such as semiconductor device performance degradation

Active Publication Date: 2021-03-30
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] Parasitic resistance and parasitic capacitance will degrade the performance of semiconductor devices

Method used

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  • Method of forming semiconductor device including conductive contacts on source/drain
  • Method of forming semiconductor device including conductive contacts on source/drain
  • Method of forming semiconductor device including conductive contacts on source/drain

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Embodiment Construction

[0032] According to embodiments of the inventive concepts, methods of forming semiconductor devices including low parasitic resistance and low parasitic capacitance contacts are provided. The method may include forming a metal layer on the source / drain to reduce parasitic resistance and forming a contact vertically overlapping only a portion of the metal layer to reduce parasitic capacitance. According to embodiments of the inventive concept, a metal layer may be formed after performing a high temperature process (eg, a replacement gate process), so that degradation of the metal layer may be reduced.

[0033] Methods and devices according to embodiments of the inventive concepts will now be discussed in more detail with reference to the accompanying drawings, in which example embodiments of these methods and semiconductor devices and intermediate structures are shown.

[0034] figure 1 is a perspective view of a semiconductor device according to some embodiments of the invent...

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Abstract

A method of forming a semiconductor device is provided. The method may include: forming a plurality of fin-shaped channels on the substrate; forming a gate structure across the plurality of fin-shaped channels; and forming a source / drain adjacent to one side of the gate structure. The source / drain may span the plurality of fin-shaped channels and may be electrically connected to the plurality of fin-shaped channels. The method may further include forming a metal layer on an upper surface of the source / drain and forming a conductive contact on the metal layer opposite to the source / drain. A first length of the conductive contact in the longitudinal direction of the metal layer may be smaller than a second length of the metal layer in the longitudinal direction of the metal layer.

Description

[0001] This application claims priority to US Application Serial No. 14 / 878,230, filed October 8, 2015, which is hereby incorporated by reference in its entirety as if filed herein. technical field [0002] The inventive concept relates generally to the field of electronics, and more particularly to semiconductor devices. Background technique [0003] Parasitic resistance and parasitic capacitance degrade the performance of semiconductor devices. With scaling, parasitic resistance and capacitance increase and may need to be reduced for high performance semiconductor devices. Contents of the invention [0004] A method of forming a semiconductor device may include: forming a plurality of fin-shaped channels on a substrate; forming a gate structure spanning the plurality of fin-shaped channels; forming a source adjacent to one side of the gate structure / drain. The source / drain may span the plurality of fin-shaped channels and may be electrically connected to the plurality...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/336H01L21/28H01L21/768
CPCH01L21/28H01L21/768H01L21/76838H01L29/66477H01L29/7848H01L29/165H01L21/28512H01L21/28518H01L23/485H01L21/76843H01L29/41791H01L29/66545H01L29/66795H01L29/665H01L29/41725
Inventor 乔治·A·吉尔咖尼时·海德沃克·森古皮塔伯纳·J·欧博阿多威马克·S·荣德
Owner SAMSUNG ELECTRONICS CO LTD