FPGA-based SDRAM control system

Abstract

The invention relates to an FPGA-based SDRAM control system. The system comprises an RAM read-write control module, an interface conversion module and an SDRAM controller IP module, wherein the interface conversion module comprises an RAM read-write control interface, a selection sub-module and at least two conversion sub-modules; the SDRAM controller IP module comprises at least two controller IP sub-modules; the at least two controller IP sub-modules are different from each other; the at least two conversion sub-modules are used for realizing conversion between an RAM interface specification and different types of SDRAM controller IP interface specifications; and the at least two conversion sub-modules are in one-to-one correspondence with the at least two controller IP sub-modules. According to the system, an SDRAM can be conveniently and quickly used in FPGAs of different manufacturers, so that the universality of the FPGAs for SDRAM control is extended.

Description

technical field [0001] The present invention relates to the technical field of FPGA (Field Programmable Gate Array, Field Programmable Gate Array), in particular to an FPGA-based SDRAM control system. Background technique [0002] SDRAM: Synchronous Dynamic Random Access Memory, that is, synchronous dynamic random access memory, which locks the CPU and RAM together through the same clock, so that RAM and CPU can share a clock cycle and work synchronously at the same speed. Compared with EDO memory The speed can be increased by 50%. SDRAM is based on a dual-bank structure and contains two interleaved memory arrays. When the CPU accesses data from one memory bank or array, the other is ready for reading and writing data. Through the close switching of the two memory arrays , the reading efficiency can be doubled. In the fields of image acquisition and data analysis, FPGA and SDRAM are often used to cache and process a large amount of data. [0003] Generally speaking, there...

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