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A Method to Accelerate the Incremental Layout Rationalization of Standard Cells

A standard cell and layout technology, applied in electrical digital data processing, special data processing applications, instruments, etc., can solve problems such as time-consuming and design rule violations in complex systems, and achieve the effect of improving efficiency and shortening time.

Active Publication Date: 2020-07-10
北京华大九天科技股份有限公司
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  • Abstract
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Problems solved by technology

For each unit that needs to be adjusted in design optimization, it is necessary to find a reasonable location in its vicinity. This is a very time-consuming operation for complex systems. If it is not handled properly, it will also cause design rule violations

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  • A Method to Accelerate the Incremental Layout Rationalization of Standard Cells
  • A Method to Accelerate the Incremental Layout Rationalization of Standard Cells
  • A Method to Accelerate the Incremental Layout Rationalization of Standard Cells

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Embodiment Construction

[0028] The preferred embodiments of the present invention will be described below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described here are only used to illustrate and explain the present invention, and are not intended to limit the present invention.

[0029] figure 1 For the method flow chart of accelerating standard cell incremental layout rationalization according to the present invention, reference will be made below figure 1 , to describe in detail the method for accelerating the rationalization of incremental layout of standard cells of the present invention.

[0030] First, in step 101, read in the physical information of the chip layout, locate the position and size of the cell row placed in the chip; read in the physical position information of each unit contained in the circuit, and determine the legal position available in the cell row; Select a certain circuit unit that needs to be incrementally laid ...

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Abstract

A method for accelerating the standard cell rationalization in incremental placement includes the steps of determining circuit units which need incremental placement, and searching for matched cell rows; searching matched cell rows near target positions, and accelerating the search process of legal positions nearest to the target positions. According to the method for accelerating the standard cell rationalization in incremental placement, the branch-and-bound method is adopted, threshold parameters are set, the second-best solution scheme in solution space is filtered out, and in incremental placement, the time for searing for the legal positions of standard cells is shortened, and the efficiency of design optimization is improved.

Description

technical field [0001] The invention relates to the technical field of EDA design, in particular to a method for finding rationalized positions of units. Background technique [0002] The back-end physical design of VLSI increasingly relies on the assistance of EDA (Electronic Design Automation) tools. Circuit design optimization requires changing the type and size of units in the circuit, inserting new units, or moving existing units. In order to ensure that the design rules are not violated, the changed cells must be legalized through layout and placed in the legal position of the cell row in the chip. How to quickly find the legal position of the unit in the incremental layout is related to the speed and quality of design optimization. [0003] Generally speaking, the physical layout of the chip contains several cell rows, that is, the physical placement of standard cells. The cells in the circuit must be placed on the cell rows and meet certain orientation and other co...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F30/392G06F30/398
CPCG06F30/392G06F30/398
Inventor 周汉斌刘毅董森华陈彬
Owner 北京华大九天科技股份有限公司
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