Implementation Method of Direct Memory Operation Based on Consistency Acceleration Interface

A realization method and consistent technology, applied in the direction of instrumentation, electrical digital data processing, etc., to achieve the effects of maximizing efficiency utilization, improving transmission reliability, and simplifying system complexity

Active Publication Date: 2019-12-10
BEIJING SIFANG JIBAO AUTOMATION
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The data written into CACHE by FPGA through ACP interface can be automatically and instantly synchronized to ARM through SCU, which solves the problem of CACHE consistency

Method used

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  • Implementation Method of Direct Memory Operation Based on Consistency Acceleration Interface
  • Implementation Method of Direct Memory Operation Based on Consistency Acceleration Interface
  • Implementation Method of Direct Memory Operation Based on Consistency Acceleration Interface

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Embodiment Construction

[0026] The technical solution of the present invention will be further introduced in detail below in conjunction with the accompanying drawings of the description.

[0027] This application discloses an active variable-length DMA implementation method based on a consistent acceleration interface, as shown in the attached image 3 shown.

[0028] Described Zynq chip is the Zynq dual-core series chip of Xilinx Company, is made up of dual-core ARM and FPGA, is connected by the advanced extensible interface (AXI) bus in chip between dual-core ARM and FPGA, and dual-core ARM and FPGA share external memory. The internal hardware structure is as figure 1 shown.

[0029] attached figure 2 In the existing processor + FPGA implementation scheme, to complete a DMA task, the processor first needs to read the summary information of the uplink data from the FPGA. The processor calculates the transmission length of the DMA based on the summary information, starts the DMA receiving task, ...

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Abstract

The invention discloses a direct memory operation implementation method based on a coherent acceleration interface. Peripherals are received inside an FPGA (field programmable gate array), received data are written into a memory in a direct memory access mode, description information of a data packet is simultaneously written into the memory, an ARM (advanced RISC machines) processor is informed in a data packet description information queue writing pointer updating mode and identifies whether a pointer is updated or not in an interrupted or inquiry mode, reading and writing pointer difference is calculated, and quantity information of the data packet to be processed is acquired. The data processing procedure includes that the description information of the data packet is firstly read, and whether to process the corresponding data packet or not is decided according to the attribute of the described data packet. The processing efficiency and flexibility of the processor are greatly improved, system complexity is simplified, and transmission reliability is correspondingly improved. The method is used for the field of control of an electric power system with large data throughout and high processing real-time requirement.

Description

technical field [0001] The invention belongs to the field of electric power system control, and is suitable for applications where a large amount of external input data is required to move and process a large amount of external data, such as digital relay protection and the like. Background technique [0002] With the continuous development and progress of substation automation technology, in smart substations, due to the promotion of information digitization, it provides the basis for various advanced applications and has become the main direction of substation automation technology development. On this basis, the data access volume of various smart devices is gradually increasing, and the requirements for the data throughput and processing capabilities of the processor are rapidly increasing with the increase in the number of high-speed data interface peripherals. [0003] The current embedded high-performance processors, such as PowerPC, DSP, etc., in order to improve the...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F13/28
CPCG06F13/28
Inventor 周涛王辉徐刚陈秋荣徐万方刘万鹏王天建孔丽
Owner BEIJING SIFANG JIBAO AUTOMATION
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