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Test circuit based on CMOS GOA

A technology for testing circuits and transistors, applied in the direction of instruments, static indicators, etc., can solve the problems of inability to output, inability to test the last stage of the transmission signal, etc.

Active Publication Date: 2017-05-31
WUHAN CHINA STAR OPTOELECTRONICS TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, when the CMOS GOA scans backwards, it cannot output the last stage (i.e., stage 1) stage pass signal as the test output signal (VT)
Therefore, such a test circuit has the defect of being unable to test the last stage transmission signal when the CMOS GOA scans backwards.

Method used

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  • Test circuit based on CMOS GOA
  • Test circuit based on CMOS GOA
  • Test circuit based on CMOS GOA

Examples

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Embodiment Construction

[0025] Hereinafter, exemplary embodiments are described in detail with reference to the accompanying drawings to make it easier for those of ordinary skill in the art to understand. Exemplary embodiments of the inventions presently claimed herein may encompass a variety of forms and are not limited to the examples shown and described herein. When inclusion of known structures and functions may obscure the present invention from those of ordinary skill in the art, descriptions of known structures and functions may be omitted for clarity, and like reference numerals denote like elements throughout the description.

[0026] image 3 is a circuit diagram of a CMOS GOA based test circuit according to an embodiment of the present invention.

[0027] refer to image 3 , the CMOS GOA-based test circuit 300 according to an embodiment of the present invention includes a first PMOS transistor 301 , a second PMOS transistor 302 , a first NMOS transistor 303 , a second NMOS transistor 30...

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Abstract

The invention provides a test circuit based on CMOS GOA. The test circuit comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor and a phase inverter, wherein the grid electrode of the first PMOS transistor is connected with a first level transmission signal end of CMOS GOA, the grid electrode of the second PMOS transistor is connected with the nth level transmission signal end of CMOS GOA, the first end of the first PMOS transistor is connected with a high level, the second end of the first PMOS transistor is connected with the first end of the second PMOS transistor, the second end of the second PMOS transistor is connected with the input end of the phase inverter, n is the total number of the level transmission signals, the grid electrode of the first NMOS transistor is connected with the first level transmission signal end of CMOS GOA, the grid electrode of the second NMOS transistor is connected with the nth level transmission signal end of CMOS GOA, the first end of the first NMOS transistor and the first end of the second NMOS transistor are connected with the input end of the phase inverter, and the second end of the first NMOS transistor and the second end of the second NMOS transistor are connected with the low level.

Description

technical field [0001] The invention relates to the field of GOA circuit design, in particular to the design of output test circuit based on CMOS GOA. Background technique [0002] In recent years, with the display trend of thinning, liquid crystal displays (LCDs), organic light emitting diodes (OLEDs) displays, etc. have been widely used in various electronic products (eg, mobile phones, notebook computers, televisions, etc.). [0003] The gate driver on array (Gate Driver On Array, GOA) technology is a technology that utilizes the existing thin film transistor liquid crystal display array manufacturing process to directly fabricate the gate drive circuit on the array substrate to realize the progressive scanning of the gate. . The application of this technology can directly fabricate the gate drive circuit around the panel, thereby reducing the production process, reducing the product cost, and improving the integration of the panel, making the panel thinner. [0004] In...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G09G3/00
CPCG09G3/006
Inventor 张启沛赵莽
Owner WUHAN CHINA STAR OPTOELECTRONICS TECH CO LTD