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Epi facet height uniformity improvement for fdsoi technologies

A facet and epitaxial growth technology, which is applied to semiconductor devices, electrical components, transistors, etc., can solve the problems of poor variability and difficulty in control of facet epitaxy

Active Publication Date: 2017-08-08
GLOBALFOUNDRIES U S INC MALTA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

For FDSOI technology, it is better to use facet epitaxy to reduce this parasitic capacitance (Ceff), but it is difficult to control
Faceted epitaxy can also suffer from poor wafer-to-wafer and lot-to-lot variability

Method used

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  • Epi facet height uniformity improvement for fdsoi technologies
  • Epi facet height uniformity improvement for fdsoi technologies
  • Epi facet height uniformity improvement for fdsoi technologies

Examples

Experimental program
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Embodiment Construction

[0016] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of example embodiments. It should be apparent, however, that example embodiments may be practiced without these specific details, or with an equivalent arrangement. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring example embodiments. Furthermore, unless otherwise indicated, all numbers expressing amounts, ratios and numerical properties of components, reaction conditions, etc. used in the specification and claims are to be understood as being modified in all instances by the term "about".

[0017] The present invention addresses and solves the problems of difficulty in controlling parasitic capacitance and wafer-to-wafer and batch-to-batch variability accompanying the formation of facet-raised source / drain epitaxial structures for the current FDSOI t...

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PUM

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Abstract

A method of controlling the facet height of raised source / drain epi structures using multiple spacers, and the resulting device are provided. Embodiments include providing a gate structure on a SOI layer; forming a first pair of spacers on the SOI layer adjacent to and on opposite sides of the gate structure; forming a second pair of spacers on an upper surface of the first pair of spacers adjacent to and on the opposite sides of the gate structure; and forming a pair of faceted raised source / drain structures on the SOI, each of the faceted source / drain structures faceted at the upper surface of the first pair of spacers, wherein the second pair of spacers is more selective to epitaxial growth than the first pair of spacers.

Description

technical field [0001] The present invention relates to the fabrication of semiconductor devices through a front-end-of-line (FEOL) process, and is especially suitable for fully depleted silicon-on-insulator (FDSOI) technology. Background technique [0002] FDSOI technology relies on overfilling the epitaxial (epi) layer to supply dopants to the source / drain, which results in extremely high parasitic capacitance (between gate and raised source / drain). For FDSOI technology, it is better to use facet epitaxy to reduce this parasitic capacitance (Ceff), but it is difficult to control. Facet epitaxy can also suffer from poor wafer-to-wafer and lot-to-lot variability. For example, facet height, Ceff, available dopants to be diffused into the channel, and silicide proximity are all variable. [0003] Therefore, there is a need for methods capable of controlling facet-lifted source / drain epitaxial formation, and devices formed thereby. Contents of the invention [0004] One as...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/84H01L21/336H01L29/78
CPCH01L21/84H01L29/6656H01L29/78H01L29/66628H01L29/66772H01L29/78654H01L29/66575H01L29/786H01L29/0649H01L29/0847H01L29/4983H01L29/7838
Inventor 乔治·罗伯特·姆芬格吴旭升
Owner GLOBALFOUNDRIES U S INC MALTA