Array base plate, display panel and display device

Abstract

The invention provides an array base plate. The array base plate comprises a under-laying base plate, a gate graphics layer, a source graphics layer and a source drain graphics layer, the gate graphics layer comprises multiple stripes of gate lines, the source drain graphics layer comprises multiple stripes of data lines, the gate lines and the data lines are arranged alternately, the array base plate is divided into multiple pixel units, the array base plate comprises a thin-film transistor arranged in the pixel units, the gate graphics layer comprises further a grid electrode of the thin film transistor, the source drain graphics layer comprises a source electrode and a drain electrode of the thin film transistor, the source graphics layer comprises an active layer of the thin-film transistor, wherein the orthographic projection of the drain electrode of the thin-film transistor on the under-laying base plate does not exceed the orthographic projection of the gate electrode of the thin film transistor on the under-laying base plate. The invention also provides a display panel and a display device. Poor display quality is not easily arisen by the display panel when displaying is conducted.

Description

technical field [0001] The present invention relates to the field of display technology, and in particular, to an array substrate, a display panel including the array substrate, and a display device including the display panel. Background technique [0002] The display device includes an array substrate. The array substrate includes a base substrate, a gate pattern layer, an active pattern layer and a source-drain pattern layer, the gate pattern layer includes a plurality of gate lines, the source-drain pattern layer includes a plurality of data lines, and a plurality of the The gate line and the plurality of data lines are intersected to divide the array substrate into a plurality of pixel units, the array substrate also includes thin film transistors arranged in the pixel units, and the gate pattern layer also includes the The gate of the thin film transistor, the source and drain pattern layer also includes the source and drain of the thin film transistor, the active pat...

AI Technical Summary

Problems solved by technology

The array substrate includes a base substrate, a gate pattern layer, an active pattern layer and a source-drain pattern layer, the gate pattern layer includes a plurality of gate lines, the source-drain pattern layer includes a plurality of data lines, and a plurality of the The gate line and the plurality of data lines are intersected to divide the array substrate into a plurality of pixel units, the array substrate also includes thin film transistors arranged in the pixel units, and the gate pattern layer also includes the The gate of the thin film transistor, the source and drain pattern layer also includes the source and drain of the thin film transistor, the active pattern layer includes the active layer of the thin film transistor, in order to ensure that there is enough space to set and The via hole for the electrical connection of the pixel electrode, therefore, the size of the drain is made relatively large, but in this case, it is easy to cause a short circuit between the source and the drain

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