Power semiconductor chip, photolithography mask thereof and exposure method of power semiconductor chip

A technology for power semiconductors and exposure methods, which is applied to microlithography exposure equipment, photolithography process exposure devices, and pattern surface photolithography processes, etc. Key dimensions and other issues to achieve the effect of reducing the number of chips, reducing the number, and improving the error

Active Publication Date: 2017-08-18
ZHUZHOU CRRC TIMES SEMICON CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0012] In view of this, the purpose of the present invention is to provide a power semiconductor chip, the photolithographic plate of the chip and its exposure method, to solve the problem that the existing chip production adopts multiple plates to be directly spliced ​​and formed, resulting in an increase in the number of photolithographic plates and an increase in cost. Large, and the key dimensions of the splicing graphics are not considered when splicing directly, which may easily cause splicing errors and cannot be applied to the technical problems of chip preparation with complex structures

Method used

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  • Power semiconductor chip, photolithography mask thereof and exposure method of power semiconductor chip
  • Power semiconductor chip, photolithography mask thereof and exposure method of power semiconductor chip
  • Power semiconductor chip, photolithography mask thereof and exposure method of power semiconductor chip

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Embodiment 1

[0074] In this embodiment, the exposure of a large-scale FRD device is taken as an example to introduce the technical solution, and an FRD device with three types of regions is taken as an example for illustration. The large-size chip mentioned in this embodiment and the following embodiments refers to the chip 200 whose lithographic pattern size is larger than the exposure field size of the current mainstream lithography machine (generally 22mm*22mm). A specific embodiment of a power semiconductor chip exposure method, comprising the following steps:

[0075] S101) as attached Figure 6 As shown, according to the size of the exposure field of the lithography machine, the large-sized chip 200 is divided into several area units 300 by the dividing line 3, and the area unit 300 is divided into corner area units according to the type of the chip 200 (as shown in the attached Figure 6 Shown in A) 4, edge area unit (as attached Figure 6 shown in B) 5 and the central area unit (...

Embodiment 2

[0088] A specific embodiment of a power semiconductor chip photolithography plate, the photolithography plate 100 is composed of more than two square area units 300, and includes: an active area pattern 101, and a scribe line pattern located on the outer peripheral edge of the active area pattern 101 102 , the area unit 300 is divided by the large-sized chip 200 graphics through the dividing line 3 . The area unit 300 is divided into any type of corner area unit 4 , edge area unit 5 or central area unit 6 according to the type of graphics, and the internal graphics of the same type of area unit 300 are completely consistent. The reticle 100 includes all types of area units 300 divided by the chip 200 , and the size of the reticle 100 is smaller than or equal to that of the chip 200 . as attached Figure 6 To attach Figure 11 In the illustrated embodiment, the area unit 300 includes three types: the corner area unit 4, the edge area unit 5 and the center area unit 6, and the...

Embodiment 3

[0092] A specific embodiment of a power semiconductor chip, manufactured by the method described in Embodiment 1, the chip 200 is a large-sized FRD chip, and the structure of the chip 200 satisfies that the graphics at the junction of each area unit 300 are perpendicular to the boundary line 3, located at The patterns of the area units 300 on both sides of the boundary line 3 are consistent within a set range, which is larger than the positioning error of the light shield 7 of the photolithography machine. Specifically, it is suitable for large-scale FRD devices with the following vertical structure, mainly requiring that the boundary line 3 between the area units 300 is located in the middle of the pattern, and the distance between the two sides of the pattern is larger than the positioning error of the light shielding plate 7, so that Graphic shifting caused by positioning errors of the shading plate 7 can be avoided.

[0093] as attached Figure 14 Shown is a schematic dia...

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Abstract

The invention discloses a power semiconductor chip, a photolithography mask thereof and an exposure method of the power semiconductor chip. The method includes: dividing a large-size chip into more than two region units according to exposure field sizes, and classifying the region units into optional one of corner region units, edge region units or central region units according to chip types, wherein the same-type region units are consistent in pattern; combining the region units into the photolithography mask, wherein the photolithography mask comprises all the types of the region units obtained by dividing the chip, and the size of the photolithography mask is smaller than or equal to the size of the chip; using a shading plate to select the corresponding region unit on the photolithography mask to expose a silicon wafer; using silicon wafer polarization and rotation of a photolithography machine to transfer the exposed region unit pattern to the corresponding positon of the silicon wafer, and using the exposure window of the shading plate, silicon wafer polarization and rotation to expose the rest of region units one by one. By the method, the technical problem that an existing chip manufacturing method adopts multiple-photolithography-mask splicing, many photolithography masks are used, cost is high, errors are easily caused during the splicing, and the existing manufacturing method cannot be applied to the manufacturing of chips with complex structures.

Description

technical field [0001] The invention relates to the technical field of power electronic device manufacturing, in particular to a spliced ​​large-size power semiconductor chip, a photolithography plate of the chip and an exposure method thereof. Background technique [0002] With the development of technology and the continuous expansion of application fields, power semiconductor devices occupy an increasingly important position in modern power electronics technology. At present, power semiconductor devices are developing in the direction of high frequency, high power, intelligence and modularization. Among them, as a key technology for the application of power semiconductor devices, how to realize the high power capacity of power semiconductor modules has become the key direction of research and development in this technical field. In order to realize the high power capacity of the power semiconductor module, in the prior art, several or even a dozen small chips are usually...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G03F7/20G03F9/00G03F1/42
CPCG03F1/42G03F7/70475G03F9/7073
Inventor 程银华刘国友王梦洁黄建伟陈辉王春祥肖强谭灿健罗海辉覃荣震
Owner ZHUZHOU CRRC TIMES SEMICON CO LTD
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