Realization method of a bch decoder and a compiler for generating the decoder

Abstract

The invention provides a BCH decoder and a realizing method of a compiler for generating same. The compiler for generating the BCH decoder performs simulation on an adopted BCH decoder algorithm according to an input BCH decoder configuration parameter and obtains output data which accurately match an actual circuit operation result of the BCH decoder, so that a user determines whether a current parameter satisfies an actual application requirement. If the requirement is satisfied, a verification platform testing excitation is obtained. Afterwards, the compiler analyzes a Galois field multiplier kind required for decoding by the BCH decoder, the topological structure and the circuit structure of each part, and generate a register transmission grade BCH decoder circuit register transmission grade description code and a testing platform code which correspond with the circuit structure, wherein the BCH decoder algorithm comprises syndrome computation, error position polynominal computation and a Chien search algorithm.

Description

technical field [0001] The invention relates to data error correction code technology, in particular to a BCH decoder and a method for realizing a compiler for generating the decoder. Background technique [0002] In digital storage and digital communication systems, due to the structural characteristics of storage media, unsatisfactory transmission channels and external interference and noise, errors will inevitably occur during digital signal transmission. The error correction code is used to find and correct a certain number of data errors by adding redundant data to the original data according to certain rules, so as to ensure the reliability of the data. [0003] With the improvement of data transmission rate, the requirements for error correction code processing performance are getting higher and higher. Because the power consumption of the decoder circuit is proportional to the square of the circuit clock frequency, in order to reduce the power consumption of the circ...

AI Technical Summary

Problems solved by technology

For an error-correcting code circuit of a specific transmission standard, how to adjust the calculation concurrency and pipeline structure of the circuit between the circuit area limited by static power consumption and the highest main frequency limited by dynamic power consumption is a challenging design task, the traditional single error-correcting code circuit structure with reconfigurable codewords, its operating frequency and circuit area have been limited by the pre-designed circuit structure that cannot be changed, so it is not suitable for the ultra-low power transmission equipment in the new generation of mobile applications needs

On the other hand, circuit redesign, verification time overhead, and increasingly tight R&D time budget caused by diverse error-correcting code pattern design requirements make the reusability of error-correcting code modules in integrated circuits more urgent.

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