Array substrate and manufacturing method thereof

Abstract

The present disclosure provides an array substrate and a method of manufacturing the same. The array substrate includes a substrate, a buffer layer, an active layer, a gate insulating layer with a second via hole, a gate, an interlayer insulating layer with a first via hole, a source electrode contacting the active layer through the first and second via holes, a planarization layer with a third via hole, a common electrode with a fourth via hole and a passivation layer sequentially disposed on the substrate, and a pixel electrode disposed on the passivation layer contacts the active layer through a fifth via hole passing through the fourth and third via holes, the interlayer insulating layer, and the gate insulating layer. According to present disclosure, static electricity generated in manufacturing is effectively prevented from being transferred to the active layer to cause Electro-Static discharge, which further improves the product quality.

Description

Technical field [0001] The invention relates to a display panel technology, in particular to a low-temperature polysilicon array substrate and a manufacturing method thereof. Background technique [0002] In the traditional manufacturing process of LTPS TFT (thin film transistor) LCD (liquid crystal display), a buffer layer, an active layer, and a gate insulating layer are formed on the substrate in sequence. , The gate, and then make an interlayer insulating layer and etch to the via holes at the source and drain ends of the active layer. The via holes expose part of the active layer, and then make the source / drain, make the flat layer, the common electrode, The passivation layer and the pixel electrode, the pixel electrode and the drain are in contact; in the traditional process, the via hole for the pixel electrode and the active layer is formed from the interlayer insulating layer and etched in the interlayer insulating layer (ILD) The active layer (poly) used to contact the...

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Problems solved by technology

[0002] In the manufacturing process of low-temperature polysilicon liquid crystal display panel (LTPS TFT (thin film transistor) LCD (liquid crystal display)) on the traditional thin film transistor array substrate, firstly, a buffer layer, an active layer, and a gate insulating layer are sequentially fabricated on the substrate. , gate, and then make an interlayer insulating layer and etch the via holes to the source and drain terminals of the active layer. The via holes will expose part of the active layer, and then make the source\drain, make a flat layer, a common electrode, The passivation layer and the pixel electrode, the pixel electrode is in contact with the drain; in the traditional process, the via hole for the pixel electrode to contact the active layer is formed from the interlayer insulating layer, etched in the interlayer insulating layer (ILD) The active layer (poly) used to contact the pixel electrode is exposed; in the subsequent process, such as source / drain (SD), flat layer (PLN), common electrode (Com ITO), passivation layer ( PV CVD), pixel electrode (Pixel ITO), will transfer the generated static electricity and easily to the active layer (polysilicon polySi), resulting in electrostatic discharge (ESD) of the active layer located at the interlayer insulating layer via hole and gate , Electro-Staticdischarge) injury, resulting in process abnormalities, affecting product quality

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